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| 型號(hào)： | DSP16410 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁(yè)數(shù)： | 181/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410 |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
125
4 Hardware Architecture
(continued)
4.14 System and External Memory Interface
(SEMI)
(continued)
4.14.7 Performance
The following terms are used in this section:
A requester, a core or the DMAU, requests the SEMI
to access external memory or the system bus.
Contention refers to multiple requests for the same
resource at the same time.
The designation ATIME refers to IATIME
(
ECON0
[11:8]—see
Table 59 on page 109
) for
accesses to the EIO space, YATIME (
ECON0
[7:4])
for accesses to the ERAM space, or XATIME
(
ECON0
[3:0]) for accesses to the EROM space.
RSETUP refers to the RSETUP field (
ECON0
[12]).
RHOLD refers to the RHOLD field (
ECON0
[14]).
WSETUP refers to the WSETUP field (
ECON0
[13]).
WHOLD refers to the WHOLD field (
ECON0
[15]).
Misaligned refers to 32-bit accesses to odd
addresses.
SLKArefers to the SLKA
5—4
fields
(
DMCON0
[9:8]—see
Table 31 on page 70
).
T
CLK
refers to one period of the internal clock CLK.
The SEMI controls and arbitrates two types of memory
accesses. The first is to external memory. The second
is to the internal I/O segment accessed via the system
bus.
Section 4.14.7.1
describes the SEMI perfor-
mance for system bus accesses.
Section 4.14.7.2 on
page 126
describes the SEMI performance for asyn-
chronous external memory accesses and
Section 4.14.7.3 on page 128
describes the SEMI per-
formance for synchronous external memory accesses.
The performance for all of these types of accesses are
summarized in
Section 4.14.7.4 on page 130
.
For the remainder of this section, unless otherwise oth-
erwise stated, the following assumptions apply:
There is only a single requester, i.e., no contention.
SEMI requests by the DMAU are from a memory-to-
memory (MMT) channel and the user program has
enabled the source look-ahead feature by setting the
appropriate SLKAfield (
Section 4.13.6
).
The source of the request (core vs. DMAU), the config-
uration of the SEMI data bus size (16-bit vs. 32-bit),
and the type of access (read vs. write) determine the
throughput of any external memory access.
Section 4.14.7.2
and
Section 4.14.7.3
describe the
performance for all combinations.
The DMAU source look-ahead feature takes advantage
of the DMAU pipeline and allows the DMAU to read
source data before completing the previous write to the
destination.
Section 4.14.7.4 on page 130
shows per-
formance figures with this feature both enabled and
disabled.
For an MMT channel, each DMAU access consists of a
read of the source location and write to the destination
location. Therefore, the DMAU performance values
stated in this section assume two operations per trans-
fer.
4.14.7.1 System Bus
The SEMI controls and arbitrates accesses to internal
I/O segment accessed via the system bus. Only 16-bit
and aligned 32-bit transfers are permitted via the sys-
tem bus. The system bus is used to access all the
memory-mapped registers in the DMAU, SIU0, SIU1,
PIU, and SEMI. See
Section 6.2.2 on page 228
for
details on the memory-mapped registers. Misaligned
32-bit accesses to internal I/O space cause undefined
results.
Table 65
specifies the minimum system bus access
time for either a single-word (16-bit) or double-word
(32-bit) access by a single requester. The SEMI pro-
cesses system bus accesses by multiple requesters at
a maximum rate of one access per CLK cycle.
For example, if a program executing in CORE0 per-
forms a read of the 16-bit
DMCON0
register, the read
requires a minimum of five CLK cycles. The access
could take longer if the SEMI is busy processing a prior
request, i.e., if there is contention. As a second exam-
ple of an S-bus transfer, assume the DMAU is moving
data between TPRAM0 and the SLM. The SLM is a
memory block accessed via the S-bus. Assuming no
contention, the DMAU can read a word from TPRAM0
and write a word to the SLM at an effective rate of two
16-bit words per two CLK cycles.
Table 65. System Bus Minimum Access Times
Access
Read
Write
Minimum Access Time
5
×
T
CLK
2
×
T
CLK
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