
Data Sheet
June 2001
DSP16410B Digital Signal Processor
224
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
6 Software Architecture
(continued)
6.2 Registers
DSP16410B registers fall into one of the following three
categories:
I
Directly program-accessible (or register-mapped)
registers are directly accessible in instructions and
are designated with lower-case bold, e.g.,
timer0
.
These registers are described in
Section 6.2.1
.
I
Memory-mapped registers are accessible at a mem-
ory address and are designated with upper-case
bold, e.g.,
DSTAT
. These registers are described in
Section 6.2.2 on page 228
.
I
Pin-accessible registers are accessible only through
the external device pins and are designated with
upper-case bold, i.e.,
ID
. Each JTAG port contains
the pin-accessible identification register,
ID
,
described in
Table 148 on page 238
. This register is
accessible via its associated JTAG port.
Note:
The program counter (
PC
) is an addressing reg-
ister not accessible to the programmer or
through external pins. The core automatically
controls this register to properly sequence the
instructions.
6.2.1 Directly Program-Accessible (Register-
Mapped) Registers
Figure 58 on page 225
depicts the directly program-
accessible (register-mapped) registers. The figure dif-
ferentiates core and off-core registers. As the figure
indicates, the
pllcon
,
pllfrq
, and
plldly
registers are
available in CORE0 only.
Note:
There is write-to-read latency associated with
the pipelined IDB. The assembler compensates
for this. See the DSP16000 Digital Signal Pro-
cessor Core nformation Manual for further
details.
As shown in
Figure 58 on page 225
, the register-
mapped registers consist of three types:
Data
registers store data either from the result of
instruction execution or from memory. Data registers
become source operands for instructions. This class of
registers also includes postincrement registers whose
contents are added to address registers to form new
addresses.
Control and Status
registers are used to determine
the state of the machine or to set different configura-
tions to control the machine.
Address
registers are used to hold memory location
pointers. In some cases, the user can treat address
registers as general-purpose data registers accessible
by data move instructions.
Table 135 on page 226
summarizes the register-
mapped registers. It lists all valid register designators
as they appear in an instruction syntax. For each regis-
ter, the table specifies its size, whether it is readable or
writable, its type, whether it is signed or unsigned, and
the hardware function block in which it is located. It also
indicates whether the register is in the core or is off-
core. Off-core register-mapped registers cannot be
stored to memory in a single instruction. For example,
the following instruction is not allowed and will generate
an error by the assembler:
*r0 = mgi
// NOT ALLOWED
To store the contents of an off-core register to memory,
first store the register to an intermediate register and
then store the intermediate register to memory. See the
example below:
a0h = mgi
*r0 = a0h
// a0h is intermediate reg.
// store mgi to memory