- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377000 > DSP16410 16-bit fixed point DSP with Flash PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP16410 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁(yè)數(shù)： | 316/373頁(yè) |
| 文件大?。?/td> | 5643K |
| 代理商： | DSP16410 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)當(dāng)前第316頁(yè)第317頁(yè)第318頁(yè)第319頁(yè)第320頁(yè)第321頁(yè)第322頁(yè)第323頁(yè)第324頁(yè)第325頁(yè)第326頁(yè)第327頁(yè)第328頁(yè)第329頁(yè)第330頁(yè)第331頁(yè)第332頁(yè)第333頁(yè)第334頁(yè)第335頁(yè)第336頁(yè)第337頁(yè)第338頁(yè)第339頁(yè)第340頁(yè)第341頁(yè)第342頁(yè)第343頁(yè)第344頁(yè)第345頁(yè)第346頁(yè)第347頁(yè)第348頁(yè)第349頁(yè)第350頁(yè)第351頁(yè)第352頁(yè)第353頁(yè)第354頁(yè)第355頁(yè)第356頁(yè)第357頁(yè)第358頁(yè)第359頁(yè)第360頁(yè)第361頁(yè)第362頁(yè)第363頁(yè)第364頁(yè)第365頁(yè)第366頁(yè)第367頁(yè)第368頁(yè)第369頁(yè)第370頁(yè)第371頁(yè)第372頁(yè)第373頁(yè)
Data Sheet
June 2001
DSP16410B Digital Signal Processor
260
Agere Systems—Proprietary
Use pursuant to Company instructions
Agere Systems Inc.
8 Signal Descriptions
(continued)
8.3 System and External Memory
Interface
(continued)
EACKN—DSP16410B Acknowledges External Bus
Request:
Negative-assertion output. The SEMI
acknowledges the request of an external device for
direct access to an asynchronous external memory by
asserting EACKN. See the description of the EREQN
pin above for details. The software can read the state
of the EACKN pin in the EACKN field (
ECON1
[5]—see
Table 60 on page 110
).
ESIZE—Size of External SEMI Bus:
Input. The exter-
nal data bus size input determines the size of the active
data bus. If ESIZE = 0, the external data bus is config-
ured as 16 bits and the SEMI uses ED[31:16] and
3-states ED[15:0]. If ESIZE = 1, the external data bus
is configured as 32 bits and the SEMI uses ED[31:0].
ERTYPE—EROM Type:
Input. The external ROM type
EROM component (selected by the EROMN enable). If
ERTYPE = 0, the EROM component is populated with
ROM or asynchronous SRAM, and the SEMI performs
asynchronous accesses to the EROM component. If
ERTYPE = 1, the EROM component is populated with
synchronous ZBTSRAM and the SEMI performs syn-
chronous accesses to the EROM component.
EXM—Boot Source:
Input. The external execution
memory input determines the active memory for pro-
gram execution after DSP16410B reset. If EXM = 0
when the RSTN pin makes a low-to-high transition,
both cores begin execution from their internal ROM
(IROM) memory at location 0x20000. If EXM = 1 when
the RSTN pin makes a low-to-high transition, both
cores begin execution from external ROM (EROM)
memory at location 0x80000. If the cores begin execu-
tion from external ROM, the SEMI arbitrates the
accesses from the two cores.
8.4 SIU0 Interface
SID0—External Serial Input Data:
Input. By default,
data is latched on the SID0 pin on a falling edge of the
input bit clock (SICK0) during a selected channel.
SOD0—External Serial Output Data:
Output. By
default, data is driven onto the SOD0 pin on a rising
edge of the output bit clock (SOCK0) during a selected
and unmasked channel. During inactive or masked
channel periods, SOD0 is 3-state.
SICK0—Input Bit Clock:
Input/output. SICK0 can be
an input (passive input clock) or an output (active input
clock). The SICK0 pin is the input data bit clock. By
default, data on SID0 is latched on a falling edge of this
clock, but the active level of this clock can be changed
by the ICKK field (
SCON10
[3]—
Table 111 on
page 188
). SICK0 can be configured via software as
an input (passive, externally generated) or an output
(active, internally generated) via the ICKA field
(
SCON10
[2]) and the ICKE field
(
SCON3
[6]—
Table 104 on page 185
).
SOCK0—Output Bit Clock:
Input/output. SOCK0 can
be an input (passive output clock) or an output (active
output clock). The SOCK0 pin is the output data bit
clock. By default, data on SOD0 is driven on a rising
edge of SOCK0 during active channel periods, but the
active level of this clock can be changed by the OCKK
field (
SCON10
[7]). SOCK0 can be configured via soft-
ware as an input (passive, externally generated) or an
output (active, internally generated) via the OCKA of
SCON10
[6]) and the OCKE field (
SCON3
[14]).
SIFS0—Input Frame Synchronization
: Input/output.
The SIFS0 signal indicates the beginning of a new
input frame. By default, SIFS0 is active-high, and a
low-to-high transition (rising edge) indicates the start of
a new frame. The active level and position of the input
frame sync relative to the first input data bit can be
changed via the IFSK field (
SCON10
[1]) and the IFS-
DLY[1:0] field (
SCON1
[9:8]—
Table 102 on page 183
),
respectively. SIFS0 can be configured via software as
an input (passive, externally generated) or an output
(active, internally generated) via the IFSA field
(
SCON10
[0]) and the IFSE field (
SCON3
[7]).
SOFS0—Output Frame Synchronization:
Input/out-
put. The SOFS0 signal indicates the beginning of a
new output frame. By default, SOFS0 is active-high,
and a low-to-high transition (rising edge) indicates the
start of a new frame. The active level and position of
the output frame sync relative to the first output data bit
can be changed via the OFSK field (
SCON10
[5]) and
the OFSDLY[1:0] field (
SCON2
[9:8]—
Table 103 on
page 184
), respectively. SOFS0 can be configured via
software as an input (passive, externally generated) or
an output (active, internally generated) via the OFSA
field (
SCON10
[4]) and the OFSE field (
SCON3
[15]).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP25-16AR | Phase-leg Rectifier Diode |
| DSP25 | Phase-leg Rectifier Diode |
| DSP25-12A | Phase-leg Rectifier Diode |
| DSP25-12AT | Phase-leg Rectifier Diode |
| DSP25-16A | Phase-leg Rectifier Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP16410C | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1629 Digital Signal Processor |
| DSP16410CG | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP16410CG Digital Signal Processor |
| DSP16411 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP16411 Digital Signal Processor |
| DSP1643 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| DSP1648C | 制造商:AGERE 制造商全稱:AGERE 功能描述:Host-Based Controller V.92 Modem Chip Set |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。