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參數(shù)資料
| 型號(hào)： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 96/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
Figure 30. Receive Block Diagram
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the phase-
locked clock remains locked on the received signal.
Individual bit cell phase corrections of the Voltage
Controlled Oscillator (VCO) are limited to 10% of the
phase difference between BCC and phase-locked
clock. Hence, input data jitter is reduced in ISRDCLK
by 10 to 1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI± inputs
after IRXCRS is asserted for an end of message.
IRXCRS de-asserts 1 to 2 bit times after the last
positive transition on the incoming message. This
initiates the end of reception cycle. The time delay from
the last rising edge of the message to IRXCRS de-
assert allows the last bit to be strobed by ISRDCLK and
transferred to the controller section, but prevents any
extra bit(s) at the end of message.
Data Decoding
The data receiver is a comparator with clocked output
to minimize noise sensitivity to the DI±/RXD± inputs.
Input error is less than ± 35 mV to minimize sensitivity
to input rise and fall time. ISRDCLK strobes the data
receiver output at 1/4 bit time to determine the value of
the Manchester bit, and clocks the data out on IRXDAT
on the following ISRDCLK. The data receiver also
generates the signal used for phase detector
comparison to the internal MENDEC voltage controlled
oscillator (VCO).
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with
the values 1010b. Clock is phase-locked to the
negative transition at the bit cell center of the second
“
0
”
in the pattern.
Since data is strobed at 1/4 bit time, Manchester transi-
tions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of
“
Jitter
Handling
”
is:
The peak deviation approaching or crossing 1/4 bit
cell position from nominal input transition, for which
the MENDEC section will properly decode data.
Attachment Unit Interface(AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which effec-
tively connects the DTE to a MAU. The differential
interface provided by the PCnet-32 controller is fully
compliant to Section 7 of ISO 8802-3 (ANSI/IEEE
802.3).
After the PCnet-32 controller initiates a transmission it
will expect to see data
“
looped-back
”
on the DI± pair
(when the AUI port is selected). This will internally gen-
erate a
“
carrier sense
”
, indicating that the integrity of
the data path to and from the MAU is intact, and that the
MAU is operating correctly. This
“
carrier sense
”
signal
must be asserted within TBD bit times after the first
transmitted bit on DO± (when using the AUI port). If
“
carrier sense
”
does not become active in response to
the data transmission, or becomes inactive before the
end of transmission, the loss of carrier (LCAR) error bit
Noise
Reject
Filter
Data
Receiver
Carrier
Detect
Circuit
Manchester
Decoder
IRXDAT*
ISRDCLK*
IRXCRS*
DI
±
/RXD
±
*
Internal signal
18219-37
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相關(guān)代理商/技術(shù)參數(shù) |
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