- 您現(xiàn)在的位置：買賣IC網 > PDF目錄366550 > Am79C965A (Advanced Micro Devices, Inc.) PCnet?-32 Single-Chip 32-Bit Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網控制器 |
| 文件頁數(shù)： | 93/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁當前第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁
Am79C965A
93
Packet Gap internal) after the last activity, before
transmitting on the media. The channel is a multidrop
communications media (with various topological
configurations permitted) which allows a single station
to transmit and all other stations to receive. If two nodes
simultaneously contend for the channel, their signals
will interact causing loss of data, defined as a collision.
It is the responsibility of the MAC to attempt to avoid
and recover from a collision, to guarantee data integrity
for the end-to-end transmission to the receiving station.
Medium Allocation
The IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3
1990) requires that the CSMA/CD MAC monitor the
medium for traffic by watching for carrier activity. When
carrier is detected, the media is considered busy, and
the MAC should defer to the existing message.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard also al-
lows optional two-part deferral after a receive
message.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
“Note:
It is possible for the PLS carrier sense indica-
tion to fail to be asserted during a collision on the me-
dia. If the deference process simply times the inter
packet gap based on this indication it is possible for a
short inter packet gap to be generated, leading to a
potential reception failure of a subsequent frame. To
enhance system robustness the following optional
measures, as specified in 4.2.8, are recommended
when Inter Frame Spacing Part 1 is other than zero:
1.
Upon completing a transmission, start timing the
interpacket gap, as soon as transmitting and car-
rier sense are both false.
2.
When timing an inter packet gap following recep-
tion, reset the inter packet gap timing if carrier
sense becomes true during the first 2/3 of the
inter-packet gap timing interval. During the final 1/
3 of the interval the timer shall not be reset to en
sure fair access to the medium. An initial period
shorter than 2/3 of the interval is permissible in
cluding zero.
The MAC engine implements the optional receive two
part deferral algorithm, with a first part inter-frame-
spacing time of 6.0 μs. The second part of the inter-
frame-spacing interval is therefore 3.6 μs.
The PCnet-32 controller will perform the two part defer-
ral algorithm as specified in Section 4.2.8 (Process
Deference). The Inter Packet Gap (IPG) timer will start
timing the 9.6 μs Inter Frame Spacing after the receive
carrier is de-asserted. During the first part deferral (In-
ter Frame Spacing Part1 - IFS1) the PCnet-32
controller will defer any pending transmit frame and
respond to the receive message. The IPG counter will
be reset to zero continuously until the carrier de-
asserts, at which point the IPG counter will resume the
9.6 μs count once again. Once the IFS1 period of 6.0
μs has elapsed, the PCnet-32 controller will begin
timing the second part deferral (Inter Frame Spacing
Part 2 - IFS2) of 3.6 μs. Once IFS1 has completed, and
IFS2 has commenced, the PCnet-32 controller will not
defer to a receive frame if a transmit frame is pending.
This means that the PCnet-32 controller will not
attempt to receive the receive frame, since it will start
to transmit, and generate a collision at 9.6 μs. The
PCnet-32 controller will guarantee to complete the
preamble (64-bit) and jam (32-bit) sequence before
ceasing transmission and invoking the random back-off
algorithm.
This transmit two part deferral algorithm is
implemented as an option which can be disabled using
the DXMT2PD bit in CSR3. Two part deferral after
transmission is useful for ensuring that severe IPG
shrinkage cannot occur in specific circumstances,
causing a transmit message to follow a receive
message so closely as to make them indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should gen-
erate the SQE Test message (a nominal 10 MHz burst
of 5-15 Bit Times duration) on the CI± pair (within 0.6 -
1.6 μs after the transmission ceases). During the time
period in which the SQE Test message is expected the
PCnet-32 controller will not respond to receive carrier
sense.
See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1)):
“
At the conclusion of the output function, the DTE
opens a time window during which it expects to see
the signal_quality_error signal asserted on the
Control In circuit. The time window begins when the
CARRIER_ STATUS becomes CARRIER_OFF. If
execution of the output function does not cause
CARRIER_ON to occur, no SQE test occurs in the
DTE. The duration of the window shall be at least
4.0 μs but no more than 8.0 μs. During the time
window, the Carrier Sense Function is inhibited.
”
The PCnet-32 controller implements a carrier sense
“
blinding
”
period within 0 μs
–
4.0 μs from de-assertion
of carrier sense after transmission. This effectively
means that when transmit two part deferral is enabled
(DXMT2PD is cleared) the IFS1 time is from 4 μs to 6
μs after a transmission. However, since IPG shrinkage
below 4 μs will rarely be encountered on a correctly
configured networks, and since the fragment size will
be larger than the 4 μs blinding window, then the IPG
counter will be reset by a worst case IPG shrinkage/
fragment scenario and the PCnet-32 controller will
defer its transmission. In addition, the PCnet-32
controller will not restart the
“
blinding
”
period if carrier
相關PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
發(fā)布緊急采購，3分鐘左右您將得到回復。