參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 165/228頁(yè)
文件大小： 1681K
代理商： AM79C965A
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Am79C965A
165
assertion of BLAST is less than
LINBC.
The value on the address bus will be
updated with appropriate values
every clock cycle during linear burst
operations, even though ADS will
not be asserted during every clock
cycle.
Certain combinations of watermark
programming
programming may create situations
where no linear bursting is possible,
or where the FIFO may be
excessively read or excessively
written. Such combinations are
declared as illegal.
and
LINBC
Combinations of watermark set-
tings and LINBC settings must obey
the following relationship:
watermark (in bytes)
3
LINBC (in
bytes)
Combinations of watermark and
LINBC settings that violate this rule
may cause unexpected behavior.
LINBC is set to the value of 001 by
H_RESET and is not affected by
S_RESET or STOP. This gives a
default linear burst length of 4
transfers = 001 x 4.
BCR19: EEPROM Control and Status
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
PVALID
EEPROM Valid status bit. This bit is
read only by the host. A value of
ONE in this bit indicates that a
PREAD operation has occurred,
and that 1) there is an EEPROM
connected to the PCnet-32
controller microwire interface pins
and 2) the contents read from the
EEPROM have passed the
checksum verification operation.
A value of ZERO in this bit indicates
that the contents of the EEPROM
are different from the contents of the
applicable PCnet-32 controller on-
board registers and/or that the
checksum for the entire 36 bytes of
EEPROM is incorrect or that no
EEPROM is connected to the
microwire interface pins.
PVALID is set to ZERO during
H_RESET and is unaffected by
S_RESET or the STOP bit.
However, following the H_RESET
operation, an automatic read of the
EEPROM will be performed. Just as
is true for the normal PREAD
command, at the end of this
automatic read operation, the
PVALID bit may be set to ONE.
Therefore, H_RESET will set the
PVALID bit to ZERO at first, but the
automatic EEPROM read operation
may later set PVALID to a ONE.
If PVALID becomes ZERO following
an EEPROM read operation (either
automatically generated after
H_RESET, or requested through
PREAD), then all EEPROM-
programmable BCR locations will be
reset to their H_RESET values.
If no EEPROM is present at the
EESK, EEDI and EEDO pins, then
all attempted PREAD commands
will terminate early and PVALID will
NOT be set. This applies to the
automatic read of the EEPROM
after H_RESET as well as to host-
initiated PREAD commands.
14
PREAD
EEPROM Read command bit. When
this bit is set to a ONE by the host,
the PVALID bit (BCR19[15]) will
immediately be reset to a ZERO and
then the PCnet-32 controller will
perform a read operation of 36 bytes
from the EEPROM through the
microwire interface. The EEPROM
data that is fetched during the read
will be stored in the appropriate
internal registers on board the
PCnet-32 controller. Upon
completion of the EEPROM read
operation, the PCnet-32 controller
will assert the PVALID bit. EEPROM
contents will be indirectly accessible
to the host through I/O read
accesses to the Address PROM
(offsets 0h through Fh) and through
I/O read accesses to other
EEPROM programmable registers.
Note that I/O read accesses from
these locations will not actually
access the EEPROM itself, but
instead will access the PCnet-32
controller
’
s internal copy of the
EEPROM contents. I/O write
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