參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 15/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
15
PIN DESCRIPTION: VESA VL-BUS MODE
Configuration Pins
JTAGSEL
JTAG Function Select
The value of this pin will asynchronously select
between JTAG Mode and Multi-Interrupt Mode.
Input
The value of this pin will asynchronously affect the
function of the JTAG
–
INTR
–
Daisy chain arbitration
pins, regardless of the state of the RESET pin and
regardless of the state of the LCLK pin. If the value is a
“
1
”
, then the PCnet-32 controller will be programmed
for JTAG mode. If the value is a
“
0
”
, then the PCnet-32
controller will be programmed for Multi-Interrupt Mode.
When programmed for JTAG mode, four pins of the
PCnet-32 controller will be configured as a JTAG (IEEE
1149.1) Test Access Port. When programmed for Multi-
Interrupt Mode, two of the JTAG pins will become
interrupts and two JTAG pins will be used for daisy
chain arbitration support. Table 3 below outlines the pin
changes that will occur by programming the JTAGSEL
pin.
Table 3. JTAG Pin Changes
The JTAGSEL pin may be tied directly to V
DD
or V
SS
. A
series resistor may be used but is not necessary.
LB/VESA
Local Bus/VESA VL-Bus Select
The value of this pin will asynchronously determine the
operating mode of the PCnet-32 controller, regardless
of the state of the RESET pin and regardless of the
state of the LCLK pin. If the LB/VESA pin is a tied to
V
DD
, then the PCnet-32 controller will be programmed
for Local Bus Mode. If the LB/VESA pin is tied to V
SS
,
then the PCnet-32 controller will be programmed for
VESA-VL Bus Mode.
Input
Note that the setting of LB/VESA determines the
functionality of the following pins (names in
parentheses are pins in 486 local bus mode): VLBEN
(Am486), RESET (RESET), LBS16 (AHOLD), LREQ
(HOLD), LGNT (HLDA), LREQI (HOLDI) and LGNTO
(HLDAO).
VLBEN
Burst Enable
This pin is used to determine whether or not bursting is
supported by the PCnet-32 device in VESA VL-Bus
mode. The VLBEN pin is sampled at every rising edge
of LCLK while the RESET pin is asserted.
Input
In VESA-VL mode (the LB/VESA pin is tied to V
SS
), if
the sampled value of VLBEN is low, then the BREADE
and BWRITE bits in BCR18 will be forced low, and the
PCnet-32 controller will never attempt to perform linear
burst reads or writes. If the sampled value of VLBEN is
high, linear burst accesses are permitted, consistent
with the values programmed into BREADE and
BWRITE.
Because of byte-duplication conventions within a 32-bit
Am386 system, the PCnet-32 controller will always pro-
duce the correct bytes in the correct byte lanes in
accordance with the Am386DX data sheet. This byte
duplication will automatically occur, regardless of the
operating mode selected by the LB/VESA pin.
The VLBEN pin may be tied directly to V
DD
or V
SS
. A
series resistor may be used but is not necessary.
The VLBEN pin need only be valid when the RESET
pin is active (regardless of the connection of the LB/
VESA pin) and may be tied to ID(3) in a VESA VL-Bus
version 1.0 system, or to the logical AND of ID(4),
ID(3), ID(1), and ID(0) in a VESA-VL-Bus version 1.1 or
2.0 system.
Note:
This pin needs to be tied low when the LB/VESA pin
has been tied to V
DD
. See the pin description for the Am486
pin in the Local Bus Mode section.
Configuration Pin Settings Summary
Table 4 shows the possible pin configurations that may
be invoked with the PCnet-32 controller configuration
pins.
Pin
JTAGSEL=1
JTAG Mode
JTAGSEL=0
Multi-Interrupt Mode
LGNT0/TCK
TCK
LGNTO
LGNT1/TDO
TDO
LREQI
LGNT2/TDI
TDI
INTR3
LGNT3/TMS
TMS
INTR4
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