參數(shù)資料
型號(hào): Am79C965A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述: PCnet?-32單芯片32位以太網(wǎng)控制器
文件頁數(shù): 139/228頁
文件大?。?/td> 1681K
代理商: AM79C965A
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Am79C965A
139
Read/write accessible only when
STOP bit is set.
7-0
RES
Reserved locations. Read and
written as zero.
CSR42: Current Transmit Status and Byte Count
Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved locations. Read and
written as zero.
11-0
CXBC
Current Transmit Byte Count. This
field is a copy of the BCNT field of
TMD2 of the current transmit
descriptor.
Read/write accessible only when
STOP bit is set.
CSR43: Current Transmit Status and Byte Count
Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
CXST
Current Transmit Status. This field is
a copy of bits 15:8 of TMD1 of the
current transmit descriptor.
Read/write accessible only when
STOP bit is set.
7-0
RES Reserved locations. Read and
written as zero.
CSR44: Next Receive Status and Byte Count
Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved locations. Read and
written as zero.
11-0
NRBC
Next Receive Byte Count. This field
is a copy of the BCNT field of RMD2
of the next receive descriptor.
Read/write accessible only when
STOP bit is set.
CSR45: Next Receive Status and Byte Count
Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
NRST
Next Receive Status. This field is a
copy of bits 15:8 of RMD1 of the next
receive descriptor.
Read/write accessible only when
STOP bit is set.
7-0
RES
Reserved locations. Read and
written as zero.
CSR46: Poll Time Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
POLL
Poll Time Counter. This counter is
incremented by the PCnet-32
controller microcode and is used to
trigger the descriptor ring polling
operation of the PCnet-32 controller.
Read/write accessible only when
STOP bit is set.
CSR47: Polling Interval
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
POLLINT Polling
Interval.
This
register
contains the time that the PCnet-32
controller will wait between
successive polling operations. The
POLLINT value is expressed as the
two
s complement of the desired
interval, where each bit of POLLINT
represents 1 BCLK period of time
(486 and VL-Bus modes; 2 BCLK
386 mode). POLLINT[3:0] are
ignored. (POLLINT[16] is implied to
be a one, so POLLINT[15] is
significant, and does not represent
the sign of the two
s complement
POLLINT value.)
The default value of this register is
0000. This corresponds to a polling
interval of 65,536 BCLK periods
(486 and VL-Bus modes; 131,072
BCLK 386 mode). The POLLINT
value of 0000 is created during the
microcode initialization routine, and
therefore might not be seen when
reading CSR47 after H_RESET or
S_RESET.
If the user desires to program a
value for POLLINT other than the
default, then the correct procedure
is to first set INIT only in CSR0.
Then, when the initialization
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