24
Am79C965A
TXDAT
Transmit Data
TXDAT is an output, providing the serial bit stream for
transmission, including preamble, SFD data and FCS
field, if applicable.
Input/Output
Note that the TxDAT pin is multiplexed with the A31 pin.
TXEN
Transmit Enable
TXEN is an output, providing an enable signal for trans-
mission. Data on the TXDAT pin is not valid unless the
TXEN signal is HIGH.
Input/Output
Note that the TXEN pin is multiplexed with the A30 pin.
STDCLK
Serial Transmit Data Clock
STDCLK is an input, providing a clock signal for MAC
activity, both transmit and receive. Rising edges of the
STDCLK can be used to validate TXDAT output data.
Input
The STDCLK pin is multiplexed with the A29 pin.
Note that this signal must meet the frequency stability
requirement of the ISO 8802-3 (IEEE/ANSI 802.3)
specification for the crystal.
CLSN
Collision
CLSN is an input, indicating to the core logic that a
collision has occurred on the network.
Input/Output
Note that the CLSN pin is multiplexed with the A28 pin.
RXCRS
Receive Carrier Sense
RXCRS is an input. When this signal is HIGH, it indi-
cates to the core logic that the data on the RXDAT input
pin is valid.
Input/Output
Note that the RXCRS pin is multiplexed with the A27
pin.
SRDCLK
Serial Receive Data Clock
SRDCLK is an input. Rising edges of the SRDCLK sig-
nal are used to sample the data on the RXDAT input
whenever the RXCRS input is HIGH.
Input/Output
Note that the SRDCLK pin is multiplexed with the A26
pin.
RXDAT
Receive Data
RXDAT is an input. Rising edges of the SRDCLK signal
are used to sample the data on the RXDAT input when-
ever the RXCRS input is HIGH.
Input/Output
Note that the RXDAT pin is multiplexed with the A25
pin.
IEEE 1149.1 Test Access Port Interface
TCK
Test Clock
The clock input for the boundary scan test mode opera-
tion. TCK can operate up to 10 MHz. If left
unconnected, this pin has a default value of HIGH.
TDI
Test Data Input
The test data input path to the PCnet-32 controller. If
left unconnected, this pin has a default value of HIGH.
TDO
Test Data Output
The test data output path from the PCnet-32 controller.
TDO is floated when the JTAG port is inactive.
TMS
Test Mode Select
A serial input bit stream is used to define the specific
boundary scan test to be executed. If left unconnected,
this pin has a default value of HIGH.
Power Supply Pins
AVDD
Analog Power (4 Pins)
There are four analog +5 Volt supply pins. Special
attention should be paid to the printed circuit board
layout to avoid excessive noise on these lines. Refer to
Appendix B and the
PCnet Family Technical Manual
(PID# 18216A)
for details.
AVSS
Analog Ground (2 Pins)
There are two analog ground pins. Special attention
should be paid to the printed circuit board layout to
avoid excessive noise on these lines. Refer to
Appendix B and the
PCnet Family Technical Manual
for
details.
DVDD
Digital Power (3 Pins)
There are 3 digital power supply pins (DVDD1, DVDD
2, and DVDD3) used by the internal digital circuitry.
DVDDCLK
Digital Power Clock (1 Pin)
This pin is used to supply power to the clock buffering
circuitry.
Input
Input
Output
Input
Power
Power
Power
Power