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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 215/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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APPENDIX D
Am79C965A
D-1
Introduction of the Look-Ahead
Packet Processing (LAPP)
Concept
A driver for the PCnet-32 controller would normally re-
quire that the CPU copy receive frame data from the
controller
’
s buffer space to the application
’
s buffer
space after the entire frame has been received by the
controller. For applications that use a ping-pong win-
dowing style, the traffic on the network will be halted
until the current frame has been completely processed
by the entire application stack. This means that the
time between last byte of a receive frame arriving at the
client
’
s Ethernet controller and the client
’
s transmission
of the first byte of the next outgoing frame will be sepa-
rated by:
1. the time that it takes the client
’
s CPU
’
s interrupt pro-
cedure to pass software control from the current
task to the driver
2. plus the time that it takes the client driver to pass the
header data to the application and request an appli-
cation buffer
3. plus the time that it takes the application to generate
the buffer pointer and then return the buffer pointer
to the driver
4. plus the time that it takes the client driver to transfer
all of the frame data from the controller
’
s buffer
space into the application
’
s buffer space and then
call the application again to process the complete
frame
5. plus the time that it takes the application to process
the frame and generate the next outgoing frame
6. plus the time that it takes the client driver to set up
the descriptor for the controller and then write a
TDMD bit to CSR0
The sum of these times can often be about the same
as the time taken to actually transmit the frames on the
wire, thereby yielding a network utilization rate of less
than 50%.
An important thing to note is that the PCnet-32 control-
ler
’
s data transfers to its buffer space are such that the
system bus is needed by the PCnet-32 controller for
approximately 4% of the time. This leaves 96% of the
sytem bus bandwidth for the CPU to perform some of
the inter-frame operations
in advance of the completion
of network receive activity
, if possible. The question
then becomes: how much of the tasks that need to be
performed between reception of a frame and transmis-
sion of the next frame can be performed
before
the re-
ception of the frame actually ends at the network, and
how can the CPU be instructed to perform these tasks
during the network reception time
The answer depends upon exactly what is happening
in the driver and application code, but the steps that
can be performed at the same time as the receive data
are arriving include as much as the first three steps and
part of the fourth step shown in the sequence above.
By performing these steps before the entire frame has
arrived, the frame throughput can be substantially in-
creased.
A good increase in performance can be expected when
the first three steps are performed before the end of the
network receive operation. A much more significant
performance increase could be realized if the PCnet-32
controller could place the frame data directly into the
application
’
s buffer space; (i.e. eliminate the need for
step four.) In order to make this work, it is necessary
that the application buffer pointer be determined before
the frame has completely arrived, then the buffer
pointer in the next desriptor for the receive frame would
need to be modified in order to direct the PCnet-32 con-
troller to write directly to the application buffer. More de-
tails on this operation will be given later.
An alternative modification to the existing system can
gain a smaller, but still significant improvement in per-
formance. This alternative leaves step four unchanged
in that the CPU is still required to perform the copy op-
eration, but it allows a large portion of the copy opera-
tion to be done before the frame has been completely
received by the controller, (i.e. the CPU can perform
the copy operation of the receive data from the PCnet-
32 controller
’
s buffer space into the application buffer
space
before
the frame data has completely arrived
from the network.) This allows the copy operation of
step four to be performed concurrently with the arrival
of network data, rather than sequentially, following the
end of network receive activity.
Outline of the LAPP Flow:
This section gives a suggested outline for a driver that
utilizes the LAPP feature of the PCnet-32 controller.
Note:
The labels in the following text are used as refer-
ences in the timeline diagram that follows.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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