參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 161/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
161
Note that the default value of CLL
after RESET is 00100b. All timing
diagrams in this document are
drawn with the assumption that this
is the value of CLL.
When VESA VL-Bus mode is
selected, then the LEADS pin
functions as if CLL = 00001b
regardless of the actual CLL setting.
CLL is set to 00100b by H_RESET
and is not affected by S_RESET or
STOP.
10 GCIC/IWBACKGenerate
Cache
Invalidation
Cycles. Ignore WBACK signal.
GCIC Generate Cache Invalidation
Cycles. When this bit is set and the
Am486 mode has been selected,
then the PCnet-32 controller
assumes that the host system
contains a cache, but the host
system does not snoop the local bus
master accesses of the PCnet-32
controller, and therefore, that cache
invalidation cycles must be
generated by the PCnet-32
controller for PCnet-32 controller
master accesses. PCnet-32
controller will not perform snoops to
invalidate cache lines for local bus
accesses that other local bus
masters may have executed. When
GCIC is a ZERO, the PCnet-32
controller assumes that logic in the
host system will create the cache
invalidation cycles that may be
necessary as a result of PCnet-32
controller local bus master
accesses. The cache invalidation
logic performs its functions
according to the GCIC and CLL bits,
regardless of the setting of the
Am486/Am386 pin.
IWBACK Ignore WBACK signal. When this bit
is set and the VESA VL-Bus Mode
has been selected, then the
PCnet-32 device will operate as
though the WBACK input pin is
always held HIGH, even though the
real value of the WBACK input may
change. This function is provided to
allow the PCnet-32 device to
operate in systems which violate
VESA VL-Bus WBACK operation by
either floating this pin or by always
driving this pin LOW.
LEADS is always asserted with each
assertion of ADS when VESA VL-
Bus mode has been selected,
regardless of the setting of the
GCIC/IWBACK bit.
GCIC/IWBACK
H_RESET and is not affected by
S_RESET or STOP.
is
cleared
by
9
PRPCNET Priority PCnet. This bit is used to set
the priority of the daisy chain
arbitration logic that resides within
the PCnet-32 controller. When
PRPCNET = 1, the priority of the
daisy chain logic is set to PCnet-32
controller highest priority, External
device lowest priority. When
PRPCNET = 0, the priority of the
daisy chain logic is set to External
device highest priority, PCnet-32
controller lowest priority. In the case
PRPCNET = 0, where the PCnet-32
controller has lower priority than the
external device and the PCnet-32
controller is preempted due to a
HOLDI request from the external
device, the PCnet-32 controller will
complete the current sequence of
accesses and then pass the HLDA
to the external device by asserting
the HLDAO signal. The HOLD
output signal from the PCnet-32
controller will not change state
during the HLDAO hand-off. If the
PCnet-32 controller is performing a
linear burst, then the PCnet-32
controller will complete the linear
burst and then pass the HLDA to the
external device through the HLDAO
signal. For more details on exact
timing of preemption events, see the
CLL Value
Portion of Address Bus Floated
During AHOLD
00000
None
00001
A31-A2
00010
A31-A3
00011
Reserved CLL Value
00100
A31-A4
00101
–
00111
Reserved CLL Values
01000
A31-A5
01001
–
01111
Reserved CLL Values
10000
A31-A6
10001
–
11111
Reserved CLL Values
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
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AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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