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參數資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網控制器 |
| 文件頁數： | 163/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
163
part from performing linear bursting
during write accesses. In no case
will the part linearly burst a
descriptor access or an initialization
access.
BWRITE is cleared by H_RESET
and is not affected by S_RESET or
STOP.
Burst Write activity is not allowed
when the BCLK frequency is >33
MHz. Linear bursting is disabled in
VL-Bus systems that operate above
this frequency by connecting the
VLBEN pin to either ID(3) (for VL-
Bus version 1.0 systems) or ID(4)
AND ID(3) AND ID(1) AND ID(0) (for
VL-Bus version 1.1 or 2.0 systems).
In Am486-style systems that have
BCLK frequencies above 33 MHz,
disabling the linear burst capability
is ideally carried out through
EEPROM bit programming, since
the EEPROM programming can be
setup for a particular machine
’
s
architecture. When the VLBEN pin
has been reset to a ZERO, then the
BWRITE bit will be forced to a value
of ZERO. Any attempt to change this
value by writing to the BWRITE bit
location will have no effect.
4-3
TSTSHDW Test Shadow bits. These bits are
used to place the PCnet-32
controller into GPSI mode.
BCR18[3] must be set to ZERO. The
operating modes possible are
indicated in Table 47.
See Table 48 for pin reconfiguration
in GPSI mode.
Note that when the GPSI mode is
invoked, only the lower 24 bits of the
address bus are available. IOAW24
(BCR21[8]) must be set to allow
slave operations. During master
accesses in GPSI mode, the
PCnet-32 controller will not drive the
upper 8 bits of the address bus with
address information.
These bits are not writable, re-
gardless of the setting of the ENTST
bit in CSR4. Values may only be
programmed to these bits through
the EEPROM read operation.
BCR18[4:3] are set to 0 by
H_RESET and are unaffected by
S_RESET or STOP.
2-0
LINBC[2:0] Linear Burst Count. The 3-bit value
in this register sets the upper limit for
the number of transfer cycles in a
Linear Burst. This limit determines
how often the PCnet-32 controller
will assert the ADS signal during
linear burst transfers. Each time that
the interpreted value of LINBC
transfers is reached, the PCnet-32
controller will assert the ADS signal
with a new valid address. The
LINBC value should contain only
one active bit. LINBC values with
more than one active bit may
produce predictable results, but
such values will not be compatible
with future AMD network controllers.
The LINBC entry is shifted by two
bits before being used by the PCnet-
32 controller. For example, the value
LINBC[2:0] = 010 is understood by
the PCnet-32 con-troller to mean
01000 = 8. Therefore, the value
LINBC[2:0] = 010 will cause the
PCnet-32 controller to issue a new
ADS every 01000b = 8 transfers.
The PCnet-32 controller may
linearly burst fewer than the value
represented by LINBC, due to other
conditions that cause the burst to
end prematurely. Therefore, LINBC
should be regarded as an upper limit
to the length of linear burst.
TSTSHDW
Value
(BCR18[4:3])
PVALID
(BCR19[15])
GPSIEN
(CSR124[4])
Operating
Mode
00
X
0
Normal
Operating
Mode
10
1
X
GPSI Mode
01
1
0
Reserved
11
1
X
Reserved
XX
0
0
Normal
Operating
Mode
XX
0
1
GPSI Mode
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相關代理商/技術參數 |
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