參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 174/228頁
文件大小： 1681K
代理商： AM79C965A
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174
Am79C965A
controller clears the OWN bit after
filling the buffer pointed to by the
descriptor entry. The host sets the
OWN bit after emptying the buffer.
Once the PCnet-32 controller or
host has relinquished ownership of
a buffer, it must not change any
field in the descriptor entry.
30
ERR
ERR is the OR of FRAM, OFLO,
CRC, or BUFF. ERR is set by the
PCnet-32 controller and cleared by
the host.
29
FRAM
FRAMING ERROR indicates that
the incoming frame contained a
non-integer multiple of eight bits
and there was an FCS error. If
there was no FCS error on the
incoming frame, then FRAM will
not be set even if there was a non
integer multiple of eight bits in the
frame. FRAM is not valid in internal
loopback mode. FRAM is valid only
when ENP is set and OFLO is not.
FRAM is set by the PCnet-32
controller and cleared by the host.
28
OFLO
OVERFLOW error indicates that
the receiver has lost all or part of
the incoming frame, due to an
inability to store the frame in a
memory buffer before the internal
FIFO overflowed. OFLO is valid
only when ENP is not set. OFLO is
set by the PCnet-32 controller and
cleared by the host.
27
CRC
CRC indicates that the receiver
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is set by the
PCnet-32 controller and cleared by
the host.
26
BUFF
BUFFER ERROR is set any time
the PCnet-32 controller does not
own the next buffer while data
chaining a received frame. This
can occur in either of two ways:
1. The OWN bit of the next buffer
is zero.
2. FIFO overflow occurred before
the PCnet-32 controller
received the STATUS
(RMD1[31:24]) of the next de-
scriptor.
If a Buffer Error occurs, an Over-
flow Error may also occur inter-
nally in the FIFO, but will not be
reported in the descriptor status
entry unless both BUFF and OFLO
errors occur at the same time.
BUFF is set by the PCnet-32
controller and cleared by the host.
25
STP
START OF PACKET indicates that
this is the first buffer used by the
PCnet-32 controller for this frame.
It is used for data chaining buffers.
STP is set by the PCnet-32
controller and cleared by the host.
24
ENP
END OF PACKET indicates that
this is the last buffer used by the
PCnet-32 controller for this frame.
It is used for data chaining buffers.
If both STP and ENP are set, the
frame fits not one buffer and there
is no data chaining. ENP is set by
the PCnet-32 controller and
cleared by the host.
23-16 RES
Reserved locations. These loca-
tions should be read and written as
ZEROs.
15-12 ONES
These four bits must be written as
ONES. They are written by the host
and unchanged by the PCnet-32
controller.
11-0
BCNT
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two
’
s complement of the length of
the buffer. This field is written by
the host and unchanged by the
PCnet-32 controller.
RMD2
Bit
Name
Description
31-24 RCC
Receive Collision Count. Indi-
cates the accumulated number of
collisions on the network since the
last frame was successfully
received, excluding collisions that
occurred during transmissions
from this node. The PCnet-32
controller implementation of this
counter may not be compatible
with the ILACC RCC definition. If
network statistics are to be
monitored, then CSR114 should
be used for the purpose of
monitoring Receive collisions
instead of these bits.
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