參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 164/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
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164
Am79C965A
Table 48. GPSI Pin Configuration
Note that linear burst operation will
only begin on certain addresses.
The general rule for linear burst
starting addresses is:
A[31:0] MOD (LINBC x 16) = 0.
Table 49 illustrates all possible
starting address values for all legal
LINBC values (only 1, 2, and 4 are
legal; other values are reserved).
Note that A[31:8] are don
’
t care
values for all addresses. (A[1:0] do
not exist within a 32 bit system,
however, they are valid bits within
the buffer pointer field of descriptor
word 0.)
Table 49. Linear Burst Cycles
Due to the beginning address
restrictions just given, it can be
shown that some portion of the
address bus will be held stable
throughout each linear burst se-
quence, while the lowest portion of
the address bus will change value
with each new cycle. The portion of
the address bus that will be held
stable during a linear burst access is
given in Table 50.
Table 50. Linear Burst Address Bus
The assertion of RDYRTN in the
place of BRDY within a linear burst
cycle will cause the linear burst to be
interrupted. In that case, the
PCnet-32 controller will revert to
ordinary two-cycle transfers, except
that BLAST will remain de-asserted
to show that linear bursting is being
requested by the PCnet-32
controller. This situation is defined
as interrupted linear burst cycles. If
BRDY is sampled as asserted
(without also sampling RDYRTN
asserted during the same access)
during interrupted linear burst
cycles, then linear bursting will
resume.
There are several events which may
cause early termination of linear
burst. Among those events are: no
more data available for transfer in
either a buffer or in the FIFO or if
either the Cycle Register (CSR80)
or the Bus Activity Timer Register
(CSR82) times out. In any of these
cases, the PCnet-32 controller will
end the Linear Burst by asserting
BLAST and then releasing the bus.
A Partial Linear Burst may have
been sent out before the assertion of
BLAST, where
“
Partial Linear Burst
”
refers to the case where the number
of data words transferred between
the last asserted ADS and the
GPSI Function
GPSI
I/O
Type
LANCE
GPSI Pin
ILACC
GPSI Pin
PCnet-32/
PCnet-ISA
GPSI Pin
PCnet-32
Pin
Number
PCnet-32
Normal
Pin Function
Transmit Data
O
TX
TXD
TXDAT
132
A31
Transmit Enable
O
TENA
RTS
TXEN
133
A30
Transmit Clock
I
TCLK
TXC
STDCLK
134
A29
Collision
I
CLSN
CDT
CLSN
137
A28
Receive Carrier Sense
I
RENA
CRS
RXCRS
138
A27
Receive Clock
I
RCLK
RXC
SRDCLK
140
A26
Receive Data
I
RX
RXD
RXDAT
141
A25
LINBC[2:0]
LBS = Linear
Burst Size
(No. of
Transfers)
Size of
Burst
(Byte)
Linear Burst
Beginning
Addresses
(A[31:6] =
Don
’
t Care)
A[5:0] =
1
2
4
4
8
16
16
32
64
00, 10, 20, 30
00, 20
00
LINBC Value
Portion of Address Bus Stable
During Linear Burst
001
010
100
A[31:4]
A[31:5]
A[31:6]
相關(guān)PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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