參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 22/228頁(yè)
文件大小： 1681K
代理商： AM79C965A
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22
Am79C965A
If SLEEP is asserted while LREQ is asserted, then the
PCnet-32 controller will perform an internal system
S_RESET and then wait for the assertion of LGNT.
When LGNT is asserted, the LREQ signal will be de-
asserted and then the PCnet-32 controller will proceed
to the power savings mode. Note that the internal
system S_RESET will not cause the LREQ signal to be
de-asserted.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power-up time, then the system must delay the
assertion of SLEEP until three LCLK cycles after the
completion of a valid pin RESET operation.
XTAL1
–
XTAL2
Crystal Oscillator Inputs
The crystal frequency determines the network data
rate. The PCnet-32 controller supports the use of
quartz crystals to generate a 20 MHz frequency
compatible with the ISO 8802-3 (IEEE/ANSI 802.3)
network frequency tolerance and jitter specifications.
See the section
External Crystal Characteristics
(in
section Manchester Encoder/Decoder) for more detail.
Input/Output
The network data rate is one-half of the crystal fre-
quency. XTAL1 may alternatively be driven using an
external CMOS level source, in which case XTAL2
must be left unconnected. Note that when the
PCnet-32 controller
is in coma mode, there is an internal 22
KW
resistor
from XTAL1 to ground. If an external source
drives XTAL1, some power will be consumed driving
this resistor. If XTAL1 is driven LOW at this time power
consumption will be minimized. In this case, XTAL1
must remain active for at least 30 cycles after the
assertion of SLEEP and de-assertion of LREQ.
Microwire EEPROM Interface
EESK
EEPROM Serial Clock
The EESK signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the microwire interface protocol. EESK is con-
nected to the microwire EEPROM
’
s Clock pin. It is con-
trolled by either the PCnet-32 controller directly during
a read of the entire EEPROM, or indirectly by the host
system by writing to BCR19, bit 1. EESK can be used
during programming of external
EEPROM-
programmable registers
that do not use the microwire
protocol as follows:
Output
When the PCnet-32 controller is performing a serial
read of the IEEE Address EEPROM through the
microwire interface, the SHFBUSY signal will serve as
a serial shift enable to allow the EEPROM data to be
serially shifted into an external device or series of de-
vices. This same signal can be used to gate the
output
of the programmed logic to avoid the problem of
releasing intermediate values to the rest of the system
board logic. The EESK signal can serve as the clock,
and EEDO will serve as the input data stream to the
programmable shift register.
EEDO
EEPROM Data Out
The EEDO signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the microwire interface protocol. EEDO is con-
nected to the microwire EEPROM
’
s Data Output pin. It
is controlled by the EEPROM during reads. It may be
read by
the host system by reading BCR19, bit 0.
Input
EEDO can be used during programming of
external
EEPROM-programmable registers
that do not use the
microwire protocol as follows:
When the PCnet-32 controller is performing a serial
read of the IEEE Address EEPROM through the
microwire interface, the SHFBUSY signal will serve as
a serial shift enable to allow the EEPROM data to be
serially shifted into an external device or series of de-
vices. This same signal can be used to gate the
output
of the programmed logic to avoid the problem of
releasing intermediate values to the rest of the system
board logic. The EESK signal can serve as the clock,
and EEDO will serve as the input data stream to the
programmable shift register.
EECS
EEPROM Chip Select
The function of the EECS signal is to indicate to the
microwire EEPROM device that it is being accessed.
The EECS signal is active high. It is controlled by either
the PCnet-32 controller during a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 2.
EEDI
EEPROM Data In
The EEDI signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. EEDI func-
tions as an output. This pin is designed to directly inter-
face to a serial EEPROM that uses the microwire
interface protocol. EEDI is connected to the microwire
EEPROM
’
s Data Input pin. It is controlled by either the
PCnet-32 controller during command portions of a read
of the entire EEPROM, or indirectly by the host system
by writing to BCR19, bit 0.
Output
Output
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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