參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 45/228頁
文件大小： 1681K
代理商： AM79C965A
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Am79C965A
45
BASIC FUNCTIONS
System Bus Interface Function
The PCnet-32 controller is designed to operate as a
Bus Master during normal operations. Some slave
accesses to the PCnet-32 controller are required in
normal operations as well. Initialization of the PCnet-32
controller is achieved through a combination of Bus
Slave accesses, Bus Master accesses and an optional
read of a serial EEPROM that is performed by the
PCnet-32 controller. The EEPROM read operation is
performed through the microwire interface. The ISO
8802-3 (IEEE/ANSI 802.3) Ethernet Address may
reside within the serial EEPROM. Some PCnet-32
controller configuration registers may also be
programmed by the EEPROM read operation.
The address PROM, on-chip board-configuration
registers, and the Ethernet controller registers occupy
32 bytes of I/O space which can be located by
modifying the I/O base address register. The default
base address can be written to the EEPROM. The
PCnet-32 controller will automatically read the I/O
Base Address from the EEPROM after H_RESET, or at
any time that the software requests that the EEPROM
should be read. When no EEPROM is attached to the
serial microwire interface, the PCnet-32 controller
detects the condition, and enters Software Relocatable
Mode. While in Software Relocatable Mode, the
PCnet-32 controller will not respond to any bus
accesses, but will snoop the bus for accesses to I/O
address 378h. When a successfully executed and
uninterrupted sequence of write operations is seen at
this location, the PCnet-32 controller will accept the
next sequence of accesses as carrying I/O Base
Address relocation and interrupt pin programming
information. After this point, the PCnet-32 controller will
begin to respond directly to accesses directed toward
offsets from the newly loaded I/O Base Address. This
scheme allows for jumperless relocatable I/O
implementations.
Software Interface
The software interface to the PCnet-32 controller is di-
vided into two parts. One part is the direct access to the
I/O resources of the PCnet-32 controller. The PCnet-32
controller occupies 32 bytes of I/O space that must be-
gin on a 32-byte block boundary. The I/O Base Address
can be changed to any 32-bit quantity that begins on a
32-byte block boundary through the function of the
Software Relocatable Mode. It can also be changed to
any 32-bit value that begins on a 32-byte block
boundary through the automatic EEPROM read
operation that occurs immediately after the H_RESET
function has completed. This read operation
automatically alters the I/O Base Address of the
PCnet-32 controller.
The 32-byte I/O space is used by the software to pro-
gram the PCnet-32 controller operating mode, to
enable and disable various features, to monitor
operating status and to request particular functions to
be executed by the PCnet-32 controller.
The other portion of the software interface is the
descriptor and buffer areas that are shared between
the software and the PCnet-32 controller during normal
network operations. The descriptor area boundaries
are set by the software and do not change during
normal network operations. There is one descriptor
area for receive activity and there is a separate area for
transmit activity. The descriptor space contains
relocatable pointers to the network packet data and it is
used to transfer packet status from the PCnet-32
controller to the software. The buffer areas are
locations that hold packet data for transmission or that
accept packet data that has been received.
Network Interfaces
The PCnet-32 controller can be connected to an 802.3
network via one of two network interfaces. The Attach-
ment Unit Interface (AUI) provides an ISO 8802-3
(IEEE/ANSI 802.3) compliant differential interface to a
remote MAU or an on-board transceiver. The
10BASE-T interface provides a twisted-pair Ethernet
port. While in auto-selection mode, the interface in use
is determined by an auto-sensing mechanism which
checks the link status on the 10BASE-T port. If there is
no active link status, then the device assumes an AUI
connection.
DETAILED FUNCTIONS
Bus Interface Unit
The bus interface unit is built of several state machines
that run synchronously to BCLK. One bus interface unit
state machine handles accesses where the PCnet-32
controller is the bus slave, and another handles ac-
cesses where the PCnet-32 controller is the bus
master. All inputs are synchronously sampled
except
ADS, M/IO, D/C, W/R and the A[31:5] bus when this
bus is an input to the PCnet-32 controller. All outputs
are synchronously generated on the rising edge of
BCLK
with the following exceptions
:
LDEV is generated asynchronously.
RDY is
driven/floated
on falling edges of BCLK, but will
change state on rising edges of BCLK.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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