參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 129/228頁
文件大小： 1681K
代理商： AM79C965A
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Am79C965A
129
masked and unable to set INTR flag
in CSR0.
Read/Write
IDONM is cleared by H_RESET or
S_RESET and is not affected by
STOP.
accessible
always.
7
RES
Reserved location. Read and written
as zeroes.
6
DXSUFLO Disable Transmit Stop on Under-
flow error.
When DXSUFLO (CSR3, bit 6) is set
to ZERO, the transmitter is turned off
when an UFLO error occurs (CSR0,
TXON = 0).
When DXSUFLO is set to ONE, the
PCnet-32 controller gracefully
recovers from an UFLO error. It
scans the transmit descriptor ring
until it finds the start of a new frame
and starts a new transmission.
Read/Write
DXSUFLO is cleared by H_RESET
or S_RESET and is not affected by
STOP.
accessible
always.
5
LAPPEN Look-Ahead
Enable. When set to a ONE, the
LAPPEN bit will cause the PCnet-32
controller to generate an interrupt
following the descriptor write
operation to the
first
buffer of a
receive frame. This interrupt will be
generated
in addition
to the interrupt
that is generated following the
descriptor write operation to the last
buffer of a receive frame. The
interrupt will be signaled through the
RINT bit of CSR0.
Packet
Processing
Setting LAPPEN to a ONE also
enables the PCnet-32 controller to
read the STP bit of receive
descriptors. The PCnet-32 controller
will use the STP information to
determine where it should begin
writing a receive frame
’
s data. Note
that while in this mode, the
PCnet-32 controller can write
intermediate frame data to buffers
whose descriptors do not contain
STP bits set to ONE. Following the
write to the last descriptor used by a
frame, the PCnet-32 controller will
scan through the next descriptor
entries to locate the next STP bit
that is set to a ONE. The PCnet-32
controller will begin writing the next
frame
’
s data to the buffer pointed to
by that descriptor.
Note that because several de-
scriptors may be allocated by the
host for each frame, and not all
messages may need all of the
descriptors that are allocated
between descriptors that contain
STP = ONE, then some descriptors/
buffers may be skipped in the ring.
While performing the search for the
next STP bit that is set to ONE, the
PCnet-32 controller will advance
through the receive descriptor ring
regardless of the state of ownership
bits. If any of the entries that are
examined during this search
indicate PCnet-32 controller
ownership of the descriptor but also
indicate STP =
“
0
”
, then the
PCnet-32 controller will RESET the
OWN bit to ZERO in these entries. If
a scanned entry indicates host
ownership with STP =
“
0
”
then the
PCnet-32 controller will not alter the
entry, but will advance to the next
entry.
When the STP bit is found to be true,
but the descriptor that contains this
setting is not owned by the
PCnet-32 controller, then the
PCnet-32 controller will stop
advancing through the ring entries
and begin periodic polling of this
entry. When the STP bit is found to
be true, and the descriptor that
contains this setting is owned by the
PCnet-32 controller, then the
PCnet-32 controller will stop
advancing through the ring entries,
store the descriptor information that
it has just read, and wait for the next
receive to arrive.
This behavior allows the host
software to preassign buffer space
in such a manner that the
“
header
”
portion of a receive frame will always
be written to a particular memory
area, and the
“
data
”
portion of a
receive frame will always be written
to a separate memory area. The
interrupt is generated when the
“
header
”
bytes have been written to
the
“
header
”
memory area.
相關PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
相關代理商/技術參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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