參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 95/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
95
Table 27. External Clock Drive Characteristics
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO±/TXD±) are
designed to operate into terminated transmission lines.
When operating into a 78 W terminated transmission
line, the transmit signaling meets the required output
levels and skew for Cheapernet, Ethernet and
IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental mode crystal oscillator provides
the basic timing reference for the MENDEC portion of
the PCnet-32 controller. The crystal is divided by two,
to create the internal transmit clock reference. Both
clocks are fed into the MENDEC
’
s Manchester Encoder
to generate the transitions in the encoded data stream.
The
internal transmit clock is used by the MENDEC to
internally
synchronize the Internal Transmit Data
(ITXDAT) from the controller and Internal Transmit
Enable (ITXEN). The internal transmit clock is also
used as a stable bit rate clock by the receive section of
the MENDEC and controller.
The oscillator requires an external ±0.01% timing refer-
ence. The accuracy requirements, if an external crystal
is used are tighter because allowance for the on-board
parasitics must be made to deliver a final accuracy of
0.01%.
Transmission is enabled by the controller. As long as
the ITXEN request remains active, the serial output of
the controller will be Manchester encoded and appear
at DO±/TXD±. When the internal request is dropped by
the controller, the differential transmit outputs go to one
of two idle states, dependent on TSEL in the Mode
Register (CSR15, bit 9):
Receiver Path
The principal functions of the Receiver are to signal the
PCnet-32 controller that there is information on the re-
ceive pair, and separate the incoming Manchester en-
coded data stream into clock and NRZ data.
The Receiver section (see Figure 30) consists of two
parallel paths. The receive data path is a zero
threshold, wide bandwidth line receiver. The carrier
path is an offset threshold bandpass detecting line
receiver. Both receivers share common bias networks
to allow operation over a wide input common mode
range.
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width rejec-
tion is proportional to transmit data rate.
The Carrier Detection circuitry detects the presence of
an incoming data frame by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock
acquisition.Clock acquisition requires a valid
Manchester bit pattern of 1010b to lock onto the
incoming message.
When input amplitude and pulse width conditions are
met at DI±/RXD±, the internal enable signal from the
MENDEC to controller (IRXCRS) is asserted and clock
acquisition cycle is initiated.
Clock Acquisition
When there is no activity at DI± (receiver is idle), the
receive oscillator is phase locked to the internal
transmit clock. The first negative clock transition (bit
cell center of first valid Manchester
“
0
”
) after IRXCRS
is asserted interrupts the receive oscillator. The
oscillator is then restarted at the second Manchester
“
0
”
(bit time 4) and phase locked to it. As a result, the
MENDEC acquires the clock from the incoming
Manchester bit pattern in bit times with a
“
1010
”
Manchester bit pattern.
ISRDCLK and IRXDAT are enabled 1/4 bit time after
clock acquisition in bit cell 5. IRXDAT is at a HIGH state
when the receiver is idle (no ISRDCLK). IRXDAT
however, is undefined when clock is acquired and may
remain HIGH or change to LOW state whenever
ISRDCLK is enabled. At 1/4 bit time through bit cell
5,the controller portion of the PCnet-32 controller sees
the first ISRDCLK transition. This also strobes in the
incoming fifth bit to the MENDEC as Manchester
“
1
”
.
IRXDAT may make a transition after the ISRDCLK
rising edge bit cell 5, but its state is still undefined. The
Manchester
“
1
”
at bit 5 is clocked to IRXDAT output at 1/
4 bit time bit cell 6.
Clock Frequency:
20 MHz ± 0.01%
Rise/Fall Time (t
R
/t
F
):
< 6 ns from 0.5 V
to V
DD
–
0.5
XTAL1 HIGH/LOW Time
(
t
HIGH
/
t
LOW
):
20 ns min
XTAL1 Falling Edge to
Falling Edge Jitter:
< ±0.2 ns at
2.5 V input (V
DD
/2)
TSEL LOW:
The idle state of DO±/TXD± yields
“
zero
”
differential to operate transformer-coupled
loads.
TSEL HIGH:
In this idle state, DO+/TXD+ is positive
with respect to DO
–
/TXD
–
(logical HIGH).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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