![](http://datasheet.mmic.net.cn/260000/Am79C965A_datasheet_15869127/Am79C965A_110.png)
110
Am79C965A
Hardware Access
PCnet-32 Controller Master Accesses
The particular signals involved in a PCnet-32 controller
bus master transfer depends upon the bus mode that
has been selected. There are two bus modes to choose
from. They are:
I
Am486 32-bit mode
I
VESA VL-Bus mode
Complete descriptions of the signals involved in bus
master transactions for each mode may be found in the
pin description section of this document. Timing dia-
grams for master accesses may be found in the block
description section for the Bus Interface Unit. This sec-
tion simply lists the types of master accesses that will
be performed by the PCnet-32 controller with respect to
data size and address information.
The PCnet-32 controller will support master accesses
only to 32-bit peripherals in Am486 environments. The
PCnet-32 controller does not support master accesses
to 16-bit peripherals in the 486 local bus mode.
The PCnet-32 controller will support master accesses
to either 32-bit or 16-bit peripherals in VESA VL-Bus
mode. Support of master accesses to 16-bit
peripherals in VESA VL-Bus mode is provided through
the LBS16 input pin.
The PCnet-32 controller is not compatible with 8-bit
systems, since there is no mode that supports
PCnet-32 controller accesses to 8-bit peripherals.
Table 35 describes all possible bus master accesses
that the PCnet-32 controller will perform. The right-
most column lists all operations that may execute the
given access.
Table 35. Master Accesses
*Cases marked with an asterisk represent extreme
boundary conditions that are the result of programming
one- and two-byte buffer sizes, and therefore will not be
seen under normal circumstances.
Note that all PCnet-32 controller master read
operations will always activate all byte enables. (Note
the exception, when LBS16 has been asserted in VL-
Bus mode, requiring a second access. In all LBS16
cases, the second access (if required) will have BE1
and BE0 disabled. Therefore, no one-, two- or three-
byte read operations are indicated in the table.
In the instance where a transmit buffer pointer address
begins on a non-double-word boundary, the pointer will
be truncated to the next double-word boundary
address that lies below the given pointer address and
the first read access from the transmit buffer will be
indicated on the byte enable signals as a four-byte read
from this address. Any data from byte lanes that lie
outside of the boundary indicated by the buffer pointer
will be discarded inside of the PCnet-32 controller.
Access
R/W
BE3
–
BE0
Possible
Instance
4-Byte Read
RD
0000
Descriptor Read or
Initialization Block
Read or
Transmit Data
Buffer Read
4-Byte Write
WR
0000
Descriptor Write or
Receive Data
Buffer Write
3-Byte Write
WR
1000
Receive Data
Buffer Write
3-Byte Write
WR
0001
Receive Data
Buffer Write
2-Byte Write
WR
1100
Receive Data
Buffer Write
2-Byte Write
WR
1001*
Receive Data
Buffer Write
2-Byte Write
WR
0011
Receive Data
Buffer Write
1-Byte Write
WR
1110
Receive Data
Buffer Write
1-Byte Write
WR
1101*
Receive Data
Buffer Write
1-Byte Write
WR
1011*
Receive Data
Buffer Write
1-Byte Write
WR
0111
Descriptor Write or
Receive Data
Buffer Write