
Am79C965A
131
Read/Write accessible. TIMER is
cleared by H_RESET or S_RESET
and is unaffected by the STOP bit.
12
DPOLL
Disable Transmit Polling. If DPOLL
is set, the Buffer Management Unit
will disable transmit polling.
Likewise, if DPOLL is cleared,
automatic transmit polling is
enabled. If DPOLL is set, TDMD bit
in CSR0 must be periodically set in
order to initiate a manual poll of a
transmit descriptor. Transmit
descriptor polling will not take place
if TXON is reset.
Read/Write accessible. DPOLL is
cleared by H_RESET or S_RESET
and is unaffected by the STOP bit.
11 APAD_XMT Auto Pad Transmit. When set,
APAD_XMT enables the automatic
padding feature. Transmit frames
will be padded to extend them to 64
bytes including FCS. The FCS is
calculated for the entire frame
including pad, and appended after
the pad field. APAD_XMT will
override the programming of the
DXMTFCS bit.
Read
APAD_XMT is reset by H_RESET or
S_RESET and is unaffected by the
STOP bit.
and
Write
accessible.
10 ASTRP_RCV Auto Strip Receive. When set,
ASTRP_RCV enables the automatic
pad stripping feature. The pad and
FCS fields will be stripped from
receive frames and not placed in the
FIFO.
Read
ASTRP_RCV is reset by H_RESET
or S_RESET and is unaffected by
the STOP bit.
and
Write
accessible.
9
MFCO
Missed Frame Counter Overflow
interrupt. Indicates the MPC
(CSR112) wrapped around. Can
be
cleared by writing a 1 to this bit. Also
cleared by H_RESET or S_RESET
or setting the STOP bit. Writing a 0
has no effect.
When MFCO is set, INTR is as-
serted if IENA = 1 and the mask bit
MFCOM is cleared.
When
(BCR20[7:0]) has been pro-
the
SWSTYLE
register
grammed to the ILACC compati-
bility mode, then this bit has no
meaning and the PCnet-32 con-
troller will never set the value of this
bit to ONE.
8
MFCOM Missed Frame Counter Overflow
Mask. If MFCOM is set, MFCO will
be unable to set INTR in CSR0. Set
to a ONE by H_RESET or
S_RESET, unaffected by the STOP
bit.
When
(BCR20[7:0]) has been pro-
grammed to the ILACC compati-
bility mode, then this bit has no
meaning and the PCnet-32 con-
troller will set the value of this bit to
a ZERO.
the
SWSTYLE
register
7
RES
Reserved location. Written as zero
and read as zero.
6
RES
Reserved location. This bit may be
written to as either a ONE or a
ZERO, but will always be read as a
ZERO. This bit has no effect on
PCnet-32 controller operation.
5
RCVCCO Receive Collision Counter Over-
flow. Indicates the Receive Collision
Counter (CSR114) wrapped around.
Can be cleared by writing a 1 to this
bit. Also cleared by H_RESET or
S_RESET or by setting the STOP
bit. Writing a 0 has no effect.
When RCVCCO is set, INTR is
asserted if IENA=1 and the mask bit
RCVCCOM is cleared.
When
(BCR20[7:0]) has been pro-
grammed to the ILACC compati-
bility mode, then this bit has no
meaning and PCnet-32 controller
will not set the value of this bit to
ONE.
the
SWSTYLE
register
4
RCVCCOM Receive Collision Counter Over-flow
Mask. If RCVCCOM is set,
RCVCCO will be unable to set INTR
in CSR0. RCVCCOM is set to a
ONE by H_RESET or S_RESET
and is not affected by STOP.
When
(BCR20[7:0]) has been pro-
grammed to the ILACC compati-
bility mode, then this bit has no
meaning and PCnet-32 controller
the
SWSTYLE
register