
148
Am79C965A
11 - 0
Upper 12 bits of the PCnet-32
controller part number, i.e. 0010
0100 0011b.
CSR92: Ring Length Conversion
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCON
Ring Length Conversion Register.
This register performs a ring length
conversion from an encoded value
as found in the initialization block to
a Two
’
s complement value used for
internal counting. By writing bits 15-
12 with an encoded ring length, a
Two
’
s complemented value is read.
The RCON register is undefined
until written.
Read/write accessible only when
STOP bit is set.
CSR94: Transmit Time Domain Reflectometry
Count
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-10 RES
Reserved locations. Read and
written as zero.
9-0
XMTTDR Time Domain Reflectometry re-
flects the state of an internal counter
that counts from the start of
transmission to the occurrence of
loss of carrier. TDR is incremented
at a rate of 10 MHz.
Read accessible only when STOP
bit is set. Write operations are
ignored. XMTTDR is cleared by
H_RESET or S_RESET.
CSR96: Bus Interface Scratch Register 0 Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SCR0
This register is shared between the
Buffer Management Unit and the
Bus Interface Unit. All Descriptor
Data communications between the
BIU and BMU are written and read
through SCR0 and SCR1 registers.
The SCR0 register is undefined until
written.
Read/write accessible only when
STOP bit is set.
CSR97: Bus Interface Scratch Register 0 Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 S CR0
This register is shared between the
Buffer Management Unit and the
Bus Interface Unit. All Descriptor
Data communications between the
BIU and BMU are written and read
through SCR0 and SCR1 registers.
The SCR0 register is undefined until
written.
Read/write accessible only when
STOP bit is set.
CSR98: Bus Interface Scratch Register 1 Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SCR1
This register is shared between the
Buffer Management Unit and the
Bus Interface Unit. All Descriptor
Data communications between the
BIU and BMU are written and read
through SCR0 and SCR1 registers.
Read/write accessible only when
STOP bit is set.
CSR99: Bus Interface Scratch Register 1 Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SCR1
This register is shared between the
Buffer Management Unit and the
Bus Interface Unit. All Descriptor
Data communications between the
BIU and BMU are written and read
through SCR0 and SCR1 registers.
Read/write accessible only when
STOP bit is set.
CSR100: Bus Time-Out
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
MERRTO This register contains the value of
the longest allowable bus latency
(interval between assertion of HOLD
and assertion of HLDA) that a slave
device may insert into a PCnet-32
controller master transfer. If this
value of bus latency is exceeded,