參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 38/228頁
文件大小： 1681K
代理商： AM79C965A
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38
Am79C965A
Table 15. Byte Duplication on Data Bus
*
Note:
Byte duplication does not apply during a LBS16
access. See Table 8.
EADS
External Address Strobe
During master write accesses in which Generate
Cache Invalidation Cycles mode has been selected,
the EADS pin will be asserted as part of the PCnet-32
controller cache invalidation cycle. Cache invalidation
cycles will occur as often as a new cache line is
reached. The cache line size can be set with the cache
line length bits of BCR18 (bits [15:11]).
HLDA
Bus Hold Acknowledge
PCnet-32 controller examines the HLDA signal to
determine when it has been granted ownership of the
bus. HLDA is active HIGH.
Output
Input
When HLDA is asserted and HOLD is being asserted
by the PCnet-32 controller, the PCnet-32 controller
assumes ownership of the local bus. However, if the
PCnet-32 controller is asserting HOLD because
HOLDI is asserted (as in a daisy chain arbitration), then
PCnet-32 controller will assert HLDAO and will not
assume ownership of the local bus.
Note that it changes polarity when the VL mode is se-
lected (see pin description of LGNT in VESA VL-Bus
Interface section).
HLDAO
Bus Hold Acknowledge Out
This signal is multiplexed with the TCK pin, and is avail-
able only when the Multi-Interrupt mode has been se-
lected with the JTAGSEL pin.
Output
An additional local bus master may daisy-chain its
HLDA signal through the PCnet-32 controller HLDAO
pin. The PCnet-32 controller will deliver a HLDAO
signal to the additional local bus master whenever the
PCnet-32 controller receives a HLDA from the CPU,
but is not simultaneously requesting the bus internally.
The second local bus master must connect its HOLD
output to the HOLDI input of the PCnet-32 controller in
order to complete the local bus daisy-chain arbitration
control.
When SLEEP is not asserted, daisy chain arbitration
signals that pass through the PCnet-32 controller will
experience a one-clock delay from input to output (i.e.
HOLDI to HOLD and HLDA to HLDAO).
While SLEEP is asserted (either in
snooze
mode or
coma
mode), if the PCnet-32 controller is configured
for a daisy chain (HOLDI and HLDAO signals have
been selected with the JTAGSEL pin), then the system
arbitration signal HLDA will be passed directly to the
daisy-chain signal HLDAO without experiencing a one-
clock delay. However, some combinatorial delay will be
introduced in this path.
Note that this pin changes polarity when VL mode has
been selected (see pin description of LGNTO in VESA
VL-Bus Interface section).
HOLD
Bus Hold Request
PCnet-32 controller asserts the HOLD pin as a signal
that it wishes to become the local bus master. HOLD is
active high. Once asserted, HOLD remains active until
HLDA has become active, independent of subsequent
assertion of SLEEP or setting of the STOP bit or
access to the S_RESET port (offset 14h).
Output
Note t hat this pin changes polarity when the VL mode
is selected (see pin description of LREQ in VESA VL-
Bus Interface section).
HOLDI
Bus Hold Request In
This signal is multiplexed with the TDO pin, and is
available only when the Multi-Interrupt mode has been
selected with the JTAGSEL pin.
Input
An additional local bus master may daisy-chain its bus
hold request signal through the PCnet-32 controller
HOLDI pin. The PCnet-32 controller will convey the
HOLDI request to the CPU via the PCnet-32 controller
HOLD output. The second local bus master must con-
nect its HLDA input to the HLDAO output of the
PCnet-32 controller in order to complete the local bus
daisy-chain arbitration control.
When SLEEP is not asserted, daisy chain arbitration
signals that pass through the PCnet-32 controller will
BE3-
BE0
DAT
[31:24]
DAT
[23:16]
DAT
[15:8]
DAT
[7:0]
1110
Undef
Undef
Undef
A
1101
Undef
Undef
A
Undef
1011
Undef
A
Undef
Copy A
0111
A
Undef
Copy A
Undef
1100
Undef
Undef
B
A
1001
Undef
C
B
Undef
0011*
D
C
Copy D
Copy C
1000
Undef
C
B
A
0001
D
C
B
Undef
0000
D
C
B
A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
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