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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 101/228頁 |
| 文件大小： | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
101
BCR2 to a ONE. This feature is typically utilized for
terminal servers, bridges and/or router products. The
EADI interface can be used in conjunction with external
logic to capture the packet destination address from the
serial bit stream as it arrives at the PCnet-32 controller,
compare the captured address with a table of stored
addresses or identifiers, and then determine whether
or not the PCnet-32 controller should accept the
packet.
The EADI interface outputs are delivered directly from
the NRZ decoded data and clock recovered by the
Manchester decoder or input into the GPSI port. This
allows the external address detection to be performed
in parallel with frame reception and address
comparison in the MAC Station Address Detection
(SAD) block of the PCnet-32 controller.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic.
SRDCLK runs only during frame reception activity.
Once a received frame commences and data and clock
are available from the decoder, the EADI logic will
monitor the alternating (
“
1,0
”
) preamble pattern until
the two ones of the Start Frame Delimiter
(
“
1,0,1,0,1,0,1,1
”
) are detected, at which point the SF/
BD output will be driven HIGH.
The SF/BD signal will initially be LOW. The assertion of
SF/BD is a signal to the external address detection
logic that the SFD has been detected and that
subsequent SRDCLK cycles will deliver packet data to
the external
logic. Therefore, when SF/BD is asserted, the
external
address matching logic should begin de-
serialization of the SRD data and send the resulting
destination address to a content addressable memory
(CAM) or other address detection device.
In order to reduce the amount of logic external to the
PCnet-32 controller for multiple address decoding sys-
tems, the SF/BD signal will toggle at each new byte
boundary within the packet, subsequent to the SFD.
This eliminates the need for externally supplying byte
framing logic.
The EAR pin should be driven LOW by the external ad-
dress comparison logic to reject a frame.
If an address match is detected by internal address
comparison with either the Physical or Logical or
broadcast Address contained within the PCnet-32
controller, then the frame will be accepted regardless of
the condition of EAR. Internal address match is
disabled when PROM (CSR15[15]) = 0, DRCVBC
(CSR15[14]) = 1, DRCVPA (CSR15[13]) = 1 and
Logical Address Filter (CSR8
–
CSR11) = 0.
When the EADISEL bit of BCR2 is set to a ONE and
internal address match is disabled, then all incoming
frames will be accepted by the PCnet-32 controller, un-
less the EAR pin becomes active during the first 64
bytes of the frame (excluding preamble and SFD). This
allows external address lookup logic approximately 58
byte times after the last destination address bit is avail-
able to generate the EAR signal, assuming that the
PCnet-32 controller is not configured to accept runt
packets. EAR will be ignored after 64 byte times after
the SFD. The frame will be accepted if EAR has not
been asserted before this time. If Runt Packet Accept
is enabled, then the EAR signal must be generated
prior to the receive message completion, if packet
rejection is to be guaranteed. Runt packet sizes could
be as short as 12 byte times (assuming 6 bytes for
source address, 2 bytes for length, no data, 4 bytes for
FCS) after the last bit of the destination address is
available. EAR must have a pulse width of at least 150
ns.
When the EADISEL bit of BCR2 is set to a ONE and the
PROM bit of the Mode Register is set to a ONE, then
all incoming frames will be accepted by the PCnet-32
controller, regardless of any activity on the EAR pin.
The EADI outputs continue to provide data throughout
the reception of a packet. This allows the external logic
to capture packet header information to determine
protocol type, inter-networking information, and other
useful data.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
are set). This configuration is useful as a semi-power-
down mode in that the PCnet-32 controller will not per-
form any power-consuming DMA operations. However,
external circuitry can still respond to
“
control
”
frames on
the
network to facilitate remote node control.
Table 29 summarizes the operation of the EADI
interface.
Table 29. EADI Operations
PROM
EAR
Required Timing
Received
Messages
1
X
No timing requirements
All Received Frames
0
1
No timing requirements
All Received Frames
0
0
Low for 150 ns within
512 bits after SFD
PCnet-32 Controller
Internal Physical and
Logical Address
Matches
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相關(guān)代理商/技術(shù)參數(shù) |
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