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參數(shù)資料
| 型號(hào)： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 119/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
119
guaranteeing that data contained within the FIFO will
not be overwritten until at least 64 bytes (512 bits) of
preamble plus address, length and data fields have
been transmitted onto the network without
encountering a collision.
If 16 total attempts (initial attempt plus 15 retries) fail,
the PCnet-32 controller sets the RTRY bit in the current
transmit TDTE in host memory (TMD2), gives up
ownership (resets the OWN bit to zero) for this frame,
and processes the next frame in the transmit ring for
transmission. Abnormal network conditions include:
I
Loss of carrier.
I
Late collision.
I
SQE Test Error (does not apply to 10BASE-T port)
None of the abnormal network conditions should not
occur on a correctly configured 802.3 network, and will
be reported if they do.
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in
the current descriptor. The OWN bit(s) in the
subsequent descriptor(s) will be reset until the STP
(the next frame) is found.
Loss of Carrier
A loss of carrier condition will be reported if the
PCnet-32 controller cannot observe receive activity
while it is transmitting on the AUI port. After the
PCnet-32 controller initiates a transmission it will
expect to see data
“
looped-back
”
on the DI± pair. This
will internally generate a
“
carrier sense,
”
indicating that
the integrity of the data path to and from the MAU is
intact, and that the MAU is operating correctly. This
“
carrier sense
”
signal must be asserted about 6 bit
times before the last transmitted bit on DO±. If
“
carrier
sense
”
does not become active in response to the data
transmission, or becomes inactive before the end of
transmission, the loss of carrier (LCAR) error bit will be
set in TMD2 after the frame has been transmitted. The
frame will not be retried on the basis of an LCAR error.
When the 10BASE-T port is selected, LCAR will be re-
ported for every frame transmitted during the Link fail
condition.
Late Collision
A late collision will be reported if a collision condition
occurs after one slot time (512 bit times) after the trans-
mit process was initiated (first bit of preamble com-
menced). The PCnet-32 controller will abandon the
transmit process for the particular frame, set Late Colli-
sion (LCOL) in the associated TMD2, and process the
next transmit frame in the ring. Frames experiencing a
late collision will not be retried. Recovery from this con-
dition must be performed by upper layer software.
SQE Test Error
During the inter packet gap time following the comple-
tion of a transmitted message, the AUI CI± pair is as-
serted by some transceivers as a self-test. The integral
Manchester Encoder/Decoder will expect the SQE Test
Message (nominal 10 MHz sequence) to be returned
via the CI± pair, within a 40 network bit time period after
DI± goes inactive (this does not apply if the 10BASE-T
port is selected). If the CI± input is not asserted within
the 40 network bit time period following the completion
of transmission, then the PCnet-32 controller will set
the CERR bit in CSR0. CERR will be asserted in
10BASE-T mode after transmit if T-MAU is in Link Fail
state. CERR will never cause INTR to be activated. It
will, however, set the ERR bit in CSR0.
Receive Operation
The receive operation and features of the PCnet-32
controller are controlled by programmable options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. this can provide flexibility in
the reception of messages using the 802.3 frame
format.
All receive frames can be accepted by setting the
PROM bit in CSR15. When PROM is set, the PCnet-32
controller will attempt to receive all messages, subject
to minimum frame enforcement. Promiscuous mode
overrides the effect of the Disable Receive Broadcast
bit on receiving broadcast frames.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established
during H_RESET is 10b which sets the threshold flag
at 64 bytes empty.
Automatic Pad Stripping
During reception of an 802.3 frame the pad field can be
stripped automatically.
ASTRP_RCV (CSR4, bit 10) = 1 enables the automatic
pad stripping feature. The pad field will be stripped be-
fore the frame is passed to the FIFO, thus preserving
FIFO space for additional frames. The FCS field will
also be stripped, since it is computed at the
transmitting station based on the data and pad field
characters, and will be invalid for a receive frame that
has had the pad characters stripped.
The number of bytes to be stripped is calculated from
the embedded length field, as defined in the ISO 8802-
3 (IEEE/ANSI 802.3) definition, contained in the frame.
The length indicates the actual number of LLC data
bytes contained in the message. Any received frame
which contains a length field less than 46 bytes will
have the pad field stripped (if ASTRP_RCV is set).
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相關(guān)代理商/技術(shù)參數(shù) |
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