參數(shù)資料
型號: Am79C965A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述: PCnet?-32單芯片32位以太網(wǎng)控制器
文件頁數(shù): 102/228頁
文件大?。?/td> 1681K
代理商: AM79C965A
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁當前第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁
102
Am79C965A
General Purpose Serial Interface (GPSI)
The PCnet-32 controller is capable of providing a
purely digital network interface in the form of the
General Purpose Serial Interface. This interface
matches the functionality provided by earlier AMD
network controller products, such as the Am7990
LANCE, Am79C90 C-LANCE, Am79C900 ILACC
controller, Am79C940 MACE controller, and
Am79C960 PCnet-ISA controller.
The GPSI interface is selected through the PORTSEL
bits of the Mode register (CSR15) and enabled through
the TSTSHDW bits of BCR18 (bits 3 and 4) or enabled
through the GPSIEN bit in CSR124 (bit 4). The possible
settings to invoke the GPSI mode are shown in Table
30.
Table 30. GPSI Mode Selection
Note that the TSTSHDW bit values are only active
when
PVALID is TRUE.
The GPSI interface is multiplexed through 7 of the
upper 8 address bits of the system bus interface.
Therefore, applications that require the use of the GPSI
interface will be limited to the use of only 24 address
bits (A[23] through A[2] plus the byte enables, which
decode into two effective address bits).
In order to prevent the PCnet-32 controller from inter-
preting the GPSI signals as address bits during the
Software Relocatable Mode and during slave
accesses, the 24-bit Software Relocatable Mode
Address 24 mode and the I/O Address Width 24 mode
of the PCnet-32 controller must be invoked. Note that if
Software Relocatable Mode is invoked, then PVALID
must have been set to ZERO, and, therefore, the GPSI
mode is not active and therefore, the Software
Relocatable Mode might assume that all 30 address
bits are visible. But in a system that uses GPSI mode,
the GPSI signals would likely all be hard-wired to the
address pins, and, therefore, even though the device
never made it into GPSI mode, it will still not be able to
see the upper address bits. Therefore, it is always
recommended that SRMA24 mode be invoked as
described in the next paragraph:
Software Relocatable Mode Address 24 mode is in-
voked by connecting the LED2/SRDCLK pin to a LOW
level during H_RESET and during the execution of the
Software Relocation operation. When the LED2/
SRDCLK pin is LOW during H_RESET and Software
Relocatable Mode, then the device will be programmed
to use 24 bits of addressing while snooping accesses
on the bus during Software Relocatable Mode; In this
case, the PCnet-32 controller will assume that bits
A[31] through A[24] are matched at all times,
regardless of the actual values on these pins.
I/O Address Width 24 mode is invoked by writing a
ONE to the IOAW24 bit of BCR21 (bit 8 of BCR21).
This can be accomplished
safely
in either of two ways:
1.
A Software Relocation operation can write a ONE
to BCR21, bit 8.
2.
A read of the EEPROM contents can write a ONE
to BCR21, bit 8, if the EEPROM contents are cor-
rectly programmed.
These two methods do NOT require a slave access to
the PCnet-32 controller, and therefore may be per-
formed in a system in which the GPSI signals are per-
manently connected to the A[31] through A[23] pins
(assuming SRMA24 mode is invoked via the LED2/
SRDCLK pin to use method 1).
The PCnet-32 controller upper address pins are recon-
figured during GPSI mode to the functions listed in
Table 31. Note that pin number 143 (A24) has no
equivalent GPSI function and should be left
unconnected when GPSI mode is enabled.
GPSI signal functions are described in the pin descrip-
tion section under the GPSI subheading.
At the time that GPSI mode is entered, the internal
MAC clock is switched from a XTAL1-derived clock to a
clock derived from the STDCLK input. The STDCLK
input determines the network data rate and therefore
must meet frequency and stability specifications.
TSTSHDW
Value
(BCR18 [4:3])
PVALID
(BCR19 [15])
GPSIEN
(CSR124[4])
Operating
Mode
00
1
0
Normal
Operating
Mode
10
1
X
GPSI Mode
01
1
0
Reserved
11
1
X
Reserved
XX
0
0
Normal
Operating
Mode
XX
0
1
GPSI Mode
相關PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
相關代理商/技術參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product