102
Am79C965A
General Purpose Serial Interface (GPSI)
The PCnet-32 controller is capable of providing a
purely digital network interface in the form of the
General Purpose Serial Interface. This interface
matches the functionality provided by earlier AMD
network controller products, such as the Am7990
LANCE, Am79C90 C-LANCE, Am79C900 ILACC
controller, Am79C940 MACE controller, and
Am79C960 PCnet-ISA controller.
The GPSI interface is selected through the PORTSEL
bits of the Mode register (CSR15) and enabled through
the TSTSHDW bits of BCR18 (bits 3 and 4) or enabled
through the GPSIEN bit in CSR124 (bit 4). The possible
settings to invoke the GPSI mode are shown in Table
30.
Table 30. GPSI Mode Selection
Note that the TSTSHDW bit values are only active
when
PVALID is TRUE.
The GPSI interface is multiplexed through 7 of the
upper 8 address bits of the system bus interface.
Therefore, applications that require the use of the GPSI
interface will be limited to the use of only 24 address
bits (A[23] through A[2] plus the byte enables, which
decode into two effective address bits).
In order to prevent the PCnet-32 controller from inter-
preting the GPSI signals as address bits during the
Software Relocatable Mode and during slave
accesses, the 24-bit Software Relocatable Mode
Address 24 mode and the I/O Address Width 24 mode
of the PCnet-32 controller must be invoked. Note that if
Software Relocatable Mode is invoked, then PVALID
must have been set to ZERO, and, therefore, the GPSI
mode is not active and therefore, the Software
Relocatable Mode might assume that all 30 address
bits are visible. But in a system that uses GPSI mode,
the GPSI signals would likely all be hard-wired to the
address pins, and, therefore, even though the device
never made it into GPSI mode, it will still not be able to
see the upper address bits. Therefore, it is always
recommended that SRMA24 mode be invoked as
described in the next paragraph:
Software Relocatable Mode Address 24 mode is in-
voked by connecting the LED2/SRDCLK pin to a LOW
level during H_RESET and during the execution of the
Software Relocation operation. When the LED2/
SRDCLK pin is LOW during H_RESET and Software
Relocatable Mode, then the device will be programmed
to use 24 bits of addressing while snooping accesses
on the bus during Software Relocatable Mode; In this
case, the PCnet-32 controller will assume that bits
A[31] through A[24] are matched at all times,
regardless of the actual values on these pins.
I/O Address Width 24 mode is invoked by writing a
ONE to the IOAW24 bit of BCR21 (bit 8 of BCR21).
This can be accomplished
safely
in either of two ways:
1.
A Software Relocation operation can write a ONE
to BCR21, bit 8.
2.
A read of the EEPROM contents can write a ONE
to BCR21, bit 8, if the EEPROM contents are cor-
rectly programmed.
These two methods do NOT require a slave access to
the PCnet-32 controller, and therefore may be per-
formed in a system in which the GPSI signals are per-
manently connected to the A[31] through A[23] pins
(assuming SRMA24 mode is invoked via the LED2/
SRDCLK pin to use method 1).
The PCnet-32 controller upper address pins are recon-
figured during GPSI mode to the functions listed in
Table 31. Note that pin number 143 (A24) has no
equivalent GPSI function and should be left
unconnected when GPSI mode is enabled.
GPSI signal functions are described in the pin descrip-
tion section under the GPSI subheading.
At the time that GPSI mode is entered, the internal
MAC clock is switched from a XTAL1-derived clock to a
clock derived from the STDCLK input. The STDCLK
input determines the network data rate and therefore
must meet frequency and stability specifications.
TSTSHDW
Value
(BCR18 [4:3])
PVALID
(BCR19 [15])
GPSIEN
(CSR124[4])
Operating
Mode
00
1
0
Normal
Operating
Mode
10
1
X
GPSI Mode
01
1
0
Reserved
11
1
X
Reserved
XX
0
0
Normal
Operating
Mode
XX
0
1
GPSI Mode