
Am79C965A
137
CSR22: Next Receive Buffer Address Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRBA
Contains the lower 16 bits of the
next receive buffer address to which
the PCnet-32 controller will store
incoming frame data.
Read/write accessible only when
STOP bit is set.
CSR23: Next Receive Buffer Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRBA
Contains the upper 16 bits of the
next receive buffer address to which
the PCnet-32 controller will store
incoming frame data.
Read/write accessible only when
STOP bit is set.
CSR24: Base Address of Receive Ring Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADR
Contains the lower 16 bits of the
base address of the Receive Ring.
Read/write accessible only when
STOP bit is set.
CSR25: Base Address of Receive Ring Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADR
Contains the upper 16 bits of the
base address of the Receive Ring.
Read/write accessible only when
STOP bit is set.
CSR26: Next Receive Descriptor Address Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRDA
Contains the lower 16 bits of the
next RDRE address pointer.
Read/write accessible only when
STOP bit is set.
CSR27: Next Receive Descriptor Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRDA
Contains the upper 16 bits of the
next RDRE address pointer.
Read/write accessible only when
STOP bit is set.
CSR28: Current Receive Descriptor Address
Lower
Bit
Name
Description
31-16 RES Reserved locations. Written as zeros and
read as undefined.
15-0
CRDA
Contains the lower 16 bits of the
current RDRE address pointer.
Read/write accessible only when
STOP bit is set.
CSR29: Current Receive Descriptor Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRDA
Contains the upper 16 bits of the
current RDRE address pointer.
Read/write accessible only when
STOP bit is set.
CSR30: Base Address of Transmit Ring Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADX
Contains the lower 16 bits of the
base address of the Transmit Ring.
Read/write accessible only when
STOP bit is set.
CSR31: Base Address of Transmit Ring Upper
Bit
Name
Description
31-16 RES
Reserved locations. Read and
written as zero.
15-0
BADX
Contains the upper 16 bits of the
base address of the Transmit Ring.
Read/write accessible only when
STOP bit is set.
CSR32: Next Transmit Descriptor Address Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.