
112
Am79C965A
Table 37. Slave Accesses
Data =
indicates the position of the active bytes.
Copy =
indicates the positions of copies of the active
bytes.
Undef =
indicates byte locations that are undefined
during the transfer.
EEPROM Microwire Access
The PCnet-32 controller contains a built-in capability
for reading and writing to an external EEPROM. This
built-in capability consists of a microwire interface for
direct connection to a microwire compatible EEPROM,
an automatic EEPROM read feature, and a user-
programmable register that allows direct access to the
microwire interface pins.
Automatic EEPROM Read Operation
Shortly after the de-assertion of the RESET pin, the
PCnet-32 controller will read the contents of the
EEPROM that is attached to the microwire
interface.The automatic EEPROM read begins with
EECS being asserted approximately 2.5 EESK periods
following the de-assertion of the RESET pin.
Because of this automatic-read capability of the
PCnet-32 controller, an EEPROM can be used to
program many of the features of the PCnet-32
controller at power-up, allowing system-dependent
configuration information to be stored in the hardware,
instead of inside of operating code. PCnet-32 controller
interrupt pins will be floated during H_RESET and will
remain floated until either the EEPROM has been
successfully read, or, following an EEPROM read
failure, a Software Relocatable Mode sequence has
been successfully executed.
If an EEPROM exists on the microwire interface, the
PCnet-32 controller will read the EEPROM contents at
the end of the H_RESET operation. The EEPROM
contents will be serially shifted into a temporary
register and then sent to various register locations on
board the PCnet-32 controller. System bus interaction
will not occur during the EEPROM read operation after
H_RESET, since H_RESET will put the PCnet-32
controller into a state that will not recognize any I/O
accesses and the PCnet-32 controller will not yet be at
an operating point that requires it to request the bus for
bus mastering.
Thirty-four bytes of the EEPROM are set aside for
PCnet-32 configuration programming and 2 bytes of
the EEPROM are set aside for user programming of
logic that is external to the PCnet-32 controller and may
or may not be pertinent to the operation of the
PCnet-32 controller within the system. The user may
gain access to the EEPROM data by snooping the
PCnet-32 controller automatic read operation. Logic
may be attached to the EEPROM interface to snoop the
entire EEPROM read operation using the microwire
signals directly, or a simpler scheme may be invoked by
taking advantage of an additional signal provided by
the PCnet-32 controller (i.e. the SHFBUSY signal).
A checksum verification is performed on the data that
is read from the EEPROM. If the checksum verification
R/W
BE3
–
BE0
D31
–
D24
D23
–
D16
D15
–
D8
D7
–
D0
Comments
RD
0000
Data
Data
Data
Data
Double word access to double word address, e.g.
300, 30C, 310 (DWIO mode only)
RD
1100
Undef
Undef
Data
Data
WIO Mode Only:
Word access to even
word address, e.g. 300, 30C, 310
RD
0011
Data
Data
Copy
Copy
WIO Mode Only:
Word access to odd
word address, e.g. 302, 30E, 312
RD
1110
Undef
Undef
Undef
Data
WIO Mode APROM Read Only:
Byte access to
lower byte of even word address, e.g. 300, 304
RD
1101
Undef
Undef
Data
Undef
WIO Mode APROM Read Only:
Byte access to
upper byte of even word address, e.g. 301, 305
RD
1011
Undef
Data
Undef
Copy
WIO Mode APROM Read Only:
Byte access to
lower byte of odd word address, e.g. 302, 306
RD
0111
Data
Undef
Copy
Undef
WIO Mode APROM Read Only:
Byte access to
upper byte of odd word address, e.g. 303, 307
WR
0000
Data
Data
Data
Data
Double word access to double word address, e.g.
300, 30C, 310 (DWIO mode only)
WR
1100
Undef
Undef
Data
Data
WIO Mode Only:
Word access to even word
address, e.g. 300, 30C, 310
WR
0011
Data
Data
Undef
Undef
WIO Mode Only:
Word access to odd word
address, e.g. 302, 30E, 312
( )