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參數(shù)資料
| 型號(hào)： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 116/228頁 |
| 文件大小： | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
Note that the first bit out of any WORD location in the
EEPROM is treated as the MSB of the register that is
being programmed. For example, the first bit out of
EEPROM WORD location 08h will be written into
BCR16[15], the second bit out of EEPROM WORD
location 08h will be written into BCR16[14], etc.
There are two checksum locations within the
EEPROM. The first is required for the EEPROM
address. This checksum will be used by AMD driver
software to verify that the ISO 8802-3 (IEEE/ANSI
802.3) station address has not been corrupted. The
value of bytes C and D should match the 16-bit sum of
bytes 0 through B and E and F. The second checksum
location
“
byte 1F
”
is not a checksum total, but is,
instead, a checksum adjustment. The value of this byte
should be such that the total 8-bit checksum for the
entire 36 bytes of EEPROM data equals the value FFh.
The checksum adjust byte is needed by the PCnet-32
controller in order to verify that the EEPROM contents
have not been corrupted.
Byte address 8h of the EEPROM map contains the
driver IRQ field. The content of this field is used by
AMD drivers to program the interrupt channel being
used by the PCnet-32. Note that the PCnet-32 interrupt
pin selection is NOT effected by this field. The interrupt
pin selection is controlled only by the appropriate bits in
BCR21. The system interrupt channel associated with
each of the PCnet-32 INTR pins is application-depend-
ent. AMD drivers utilize byte location 8h of the
EEPROM to resolve this dependency.
EEPROM-Programming of System Logic
When the user has shareable hardware resources in
the system and wishes to have these resources pro-
grammed at power up, the user may desire to take ad-
vantage of the extra space in the EEPROM that is used
to configure the PCnet-32 controller in order to store
the additional configuration information. The PCnet-32
controller provides a convenient means of access for
the user who wishes to utilize this space. The
schematic in Figure 34 illustrates an example of logic
that is used to generate static control signals for some
programmable features of the system, where the
programming information is stored on board the
PCnet-32 controller
’
s EEPROM and the logic is to be
automatically programmed after RESET.
Note that the EECS signal pulses low during the
EEPROM read operation and is therefore unsuitable for
use as a gate signal for the programmable logic
outputs. PCnet-32 controller provides an additional
signal, SHFBUSY, which will remain active HIGH
during the entire EEPROM read operation. This signal
will therefore be suitable for use as the gate of the
programmable logic outputs as shown in the diagram.
Note that since most of the EEPROM microwire
interface signals are multiplexed with other PCnet-32
controller functions, it is necessary for the SHFBUSY
pin to enable the shift path of the programmable logic,
otherwise the shift path would become active when the
EESK and EEDO functions were operating as their
alternate functions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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