參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 46/228頁
文件大小： 1681K
代理商： AM79C965A
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46
Am79C965A
The following sections describe the various bus master
and bus slave operations that will be performed by the
PCnet-32 controller. The timing diagrams that are in-
cluded in these sections (
Bus Acquisition
section
through
Slave Timing
section) show the signals and
timings of the Am486 32-bit mode of operation. The
sections from Bus Acquisition through Linear Burst
DMA Transfers show bus master operations. The
Slave
Timing
section shows bus slave operations. Note that
the PCnet-32 controller operation in Am486 32-bit
mode represents a merger of the requirements of the
VESA VL-Bus specification and Am486 bus
specification,
whichever is more stringent. The concepts
discussed in
the following sections and the basic nature
of the timings shown is applicable in a general sense to
PCnet-32 controller operational modes. For specific
differences in timing between modes and for examples
of timing diagrams showing basic transfers in each of
the modes, please consult the following sections:
Am486 32-bit mode:
Bus Acquisition
section
through
Slave Timing
section
VESA VL-Bus mode:
VESA VL-Bus Mode Timing
section
For selection of each mode, consult the section on
Configuration Pins in the
Pin Description
section.
Note that all timing diagrams in this document have
been drawn showing reference to two groups of
address pins: namely, A4
–
A31 and A2
–
A3, BE0
–
BE3.
In the AHOLD timing diagrams, the two groups are
shown separately, because the upper address pins
become floated, while the lower address pins do not.
The point of division between the two groups of
address pins will depend upon the value of CLL in
BCR18. In the case of Linear Burst operations, the
upper address pins are shown separately because that
group does not change its value through a single linear
burst, while the lower address pins do change value. In
this case, the point of division between the two groups
of address pins will depend upon the value of LINBC in
BCR18. In all other timing diagrams, the two groups are
shown separately just to maintain consistency with the
AHOLD and Linear Burst timing diagrams. For more
details, see the AHOLD and Linear Burst Count
sections.
Bus Acquisition
The PCnet-32 controller microcode (in the buffer man-
agement section) will determine when a DMA transfer
should be initiated. The first step in any PCnet-32 con-
troller bus master transfer is to acquire ownership of the
bus. This task is handled by synchronous logic within
the BIU. Bus ownership is requested with the HOLD
signal and ownership is granted by the CPU (or an
arbiter) through the HLDA signal. The PCnet-32
controller additionally supplies HOLDI and HLDAO
signals to allow daisy chaining of devices through the
PCnet-32 controller. Priority of the HOLDI input versus
the PCnet-32 controller
’
s own internal request for bus
mastership can be set using the PRPCNET bit of
BCR17. Simple bus arbitration (HOLD, HLDA only) is
shown in Figure 1.
Note that assertion of the STOP bit will
not
cause a de-
assertion of the HOLD signal. Note also that a read of
the S_RESET register (I/O resource at offset 14h from
the PCnet-32 controller base I/O address) will
not
cause a de-assertion of the HOLD signal. Either of
these actions will cause the internal master state
machine logic to cease operations, but the HOLD
signal will remain active until the HLDA signal is
synchronously sampled as asserted. Following either
of the above actions, on the next clock cycle after the
HLDA signal is synchronously sampled as asserted,
the PCnet-32 controller will de-assert the HOLD signal.
No bus master accesses will have been performed
during this brief bus ownership period.
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