參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 169/228頁
文件大小： 1681K
代理商： AM79C965A
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁當(dāng)前第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁
Am79C965A
169
must always begin on a double-word
boundary.
The value of SSIZE32 is deter-
mined by the PCnet-32 controller.
SSIZE32 is read only by the host.
The PCnet-32 controller uses the
setting of the Software Style
register(BCR20[7:0]/CSR58[7:0]) to
determine the value for this bit.
SSIZE32 is cleared by H_RESET
and is not affected by S_RESET or
STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be used to
generate values for the upper 8 bits
of the 32 bit address bus during
master accesses initiated by the
PCnet-32 controller. This action is
required, since the 16-bit software
structures specified by the
SSIZE32=0 setting will yield only 24
bits of address for PCnet-32
controller bus master accesses.
If SSIZE32 is set, then the software
structures that are common to the
PCnet-32 controller and the host
system will supply a full 32 bits for
each address pointer that is needed
by the PCnet-32 controller for
performing master accesses.
The value of the SSIZE32 bit has no
effect on the drive of the upper 8
address pins. The upper 8 address
pins are always driven, regardless of
the state of the SSIZE32 bit.
Note:
The setting of the SSIZE32 bit has
no effect on the defined width for I/O re-
sources.I/O resource width is deter-
mined by the state of the DWIO bit.
SWSTYLE Software Style register. The value in
this register determines the
“
style
”
of
I/O and memory resources that shall
be used by the PCnet-32 controller.
The Software Style selection will af-
fect the interpretation of a few bits
within the CSR space and the width
of the descriptors and initialization
block. See Table 53.
7-0
All PCnet-32 controller CSR bits and
BCR bits and all descriptor, buffer
and initialization block entries not
cited in the table above are
unaffected by the Software Style
selection and are therefore always
fully functional as specified in the
CSR and BCR and descriptor
sections.
Read/write accessible only when
the STOP bit is set.
The SWSTLYE register will contain
the value 00h following H_RESET
and is not affected by S_RESET or
STOP.
BCR21: Interrupt Control
Bit
Name
Description
Note that all bits in this register are
programmable through the
EEPROM PREAD operation and
software relocatable mode.
31-9
RES
Reserved locations. Written as
ZEROs and read as undefined.
8
IOAW24 I/O Address Width 24 bits. When set
to a ONE, the IOAW24 bit will cause
the PCnet-32 controller to ignore the
upper 8 bits of the address bus
when determining whether an I/O
address matches PCnet-32
controller I/O space. When IOAW24
is set to a ZERO, then the PCnet-32
controller will examine all 32 bits of
the address bus when determining
whether an I/O address matches
PCnet-32 controller I/O space.
Read/write accessible only when
the STOP bit is set.
The IOAW24 bit will be reset to
ZERO by H_RESET and is not
affected by S_RESET or STOP.
7
REJECTDIS Reject Disable. When set to a
ONE, the REJECTDIS bit will cause
the EAR function of the EADI
interface to be disabled. Specifically,
the INTR2 pin will retain its function
as INTR2 and will not function as
EAR, regardless of the setting of the
BCR2 EADISEL bit. When reset to a
ZERO, the REJECTDIS bit will allow
the INTR2 pin to be redefined to
function as EAR of the EADI
interface when the EADISEL bit of
BCR2 has been set to a ONE.
Read/write accessible only when
STOP bit is set.
The REJECTDIS bit will be reset to
ZERO by H_RESET and is not
affected by S_RESET or STOP.
相關(guān)PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*