參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 105/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
105
one Vendor Specific Word is needed, it is suggested
that the VSW location should be divided into a VSW
Register Address Pointer (VSWRAP) at one location
(e.g. VSWRAP at byte location 18h) and a VSW Data
Port (VSWDP) at the other location (e.g. VSWDP at
byte location 19h). Alternatively, the system may
capture RAP data accesses in parallel with the
PCnet-32 controller and therefore share the PCnet-32
controller RAP to allow expanded VSW space.
PCnet-32 controller will not respond to access to the
VSW I/O address.
DWIO I/O Resource Map
When the PCnet-32 controller I/O space is mapped as
Double Word I/O, then all of the resources that are
allotted to the PCnet-32 controller occur on double
word boundaries that are offset from the PCnet-32
controller I/O Base Address as shown in Table 33.
Table 33. Double Word I/O Mapping
When PCnet-32 controller I/O space is Double Word-
mapped, all I/O resources fall on double word
boundaries. Address PROM resources are double
word quantities in DWIO mode. RDP, RAP and BDP
contain only two bytes of valid data. The other two
bytes of these resources are
reserved
for future use.
The reserved bits must be written as zeros, and when
read, are considered
undefined
.
Accesses to non-double word address boundaries are
not allowed while in DWIO mode. The PCnet-32
controller may or may not produce an LDEV and a RDY
signal in response to such accesses, but data will be
undefined.
Accesses of less than 4 bytes to any I/O resource are
not allowed while in DWIO mode (i.e. PCnet-32
controller will not respond to such accesses. PCnet-32
controller will not produce an LDEV and a RDY signal
in response to such accesses), but data will be
undefined. A double word write access to the RDP
offset of 10h will automatically program DWIO mode.
Note that in all cases when I/O resource width is
defined as 32 bits, the upper 16 bits of the I/O resource
is reserved and written as ZEROs and read as
undefined, except for the APROM locations and
CSR88.
DWIO mode is exited by asserting the RESET pin. As-
sertion of S_RESET or setting the STOP bit of CSR0
will have no effect on the DWIO mode setting.
I/O Space Comments
The following statements apply to both WIO and DWIO
mapping:
The RAP is shared by the RDP and the BDP.
The PCnet-32 controller does not respond to any ad-
dresses outside of the offset range 0h-17h when DWIO
= 0 or 0h-1F when DWIO = 1. I/O offsets 18h through
1Fh are not used by the PCnet-32 controller when
programmed for DWIO = 0 mode. Locations 1Ah
through 1Fh are reserved for future AMD use and
therefore should not be implemented by the user if
upward compatibility to future AMD devices is desired.
Note that Address PROM accesses do not directly ac-
cess the EEPROM, but are redirected to a set of
shadow registers on board the PCnet-32 controller that
contain a copy of the EEPROM contents that was
obtained during the automatic EEPROM read
operation that follows the RESET operation.
PCnet-32 Controller I/O Base Address
The I/O Base Address Registers (BCR16 and BCR17)
will reflect the current value of the base of the
PCnet-32 controller I/O address space. BCR16
contains the lower 16 bits of the 32-bit I/O base
address for the PCnet-32 controller. BCR17 contains
the upper 16 bits of the 32-bit I/O base address for the
PCnet-32 controller. This set of registers is both
readable and writable by the host. The value contained
in these registers is affected through three means:
1.
Immediately
following
the H_RESET operation,
the I/O Base Address will be determined by the
EEPROM read operation. During this operation,
the I/O Base Address register will become pro-
grammed with the value of the I/O Base Address
field of the EEPROM.
2.
If no EEPROM exists, or if an error is detected in
the EEPROM data, then the PCnet-32 controller
will enter
Software Relocatable Mode
. While in
this mode, the PCnet-32 controller will not
respond to any I/O accesses directly. However, the
PCnet-32
controller will snoop accesses on the system
bus.
When the PCnet-32 controller detects a spe-
cific sequence of four write accesses to I/O
address 378h, then the PCnet-32 controller will
assume that the software is attempting to relocate
the PCnet-32 controller. On eight subsequent
write accesses to I/O address 378h, the PCnet-32
controller will accept the data on the bus as a new
I/O Base Address and other programming infor-
Offset
(Hex)
No. of
Bytes
Register
0
4
Address PROM
4
4
Address PROM
8
4
Address PROM
C
4
Address PROM
10
4
RDP
14
4
RAP (shared by RDP and BDP)
18
4
Reset Register
1C
4
BDP
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