參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 122/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
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122
Am79C965A
By default, after H_RESET, the 4 LED outputs are
configured as shown in Table 40.
Table 40. LED Configuration
For each LED register, each of the status signals is
ANDed with its enable signal, and these signals are all
OR
’
d together to form a combined status signal. Each
LED pin
’
s combined status signal runs to a pulse
stretcher, which consists of a 3-bit shift register clocked
at 38 Hz (26 ms). The data input of each shift register
is normally at logic 0. The OR gate output for each LED
register asynchronously sets all three bits of its shift
register when the output becomes asserted. The
inverted output of each shift register is used to control
an LED pin. Thus the pulse stretcher provides 2
–
3
clocks of stretched LED output, or 52 ms to 78 ms.
Figure 37 shows the LED signal circuit that exists for
each LED pin.
Figure 37. On-Chip LED Control Logic
H_RESET, S_RESET and STOP
There are three different types of RESET operations
that may be performed on the PCnet-32 device,
H_RESET, S_RESET and STOP. These names have
been used throughout the document. The following is a
description of each type of RESET operation:
H_RESET
H_RESET= HARDWARE_RESET is a PCnet-32
RESET operation that has been created by the proper
assertion of the RESET pin of the PCnet-32 device.
When the minimum pulse width timing as specified in
the RESET pin description has been satisfied, then an
internal RESET operation will be performed.
H_RESET will RESET all of or some portions of CSR0,
3, 4, 15, 58, 80, 82, 100, 112, 114, 122, 124 and 126 to
default values; H_RESET will RESET all of or some
portions of BCR 2, 4, 5, 6, 7, 18, 19, 20, 21 to default
values. H_RESET will cause the microcode program to
jump to its RESET state. Following the end of the
H_RESET operation, the PCnet-32 controller will
attempt to read the EEPROM device through the
EEPROM microwire interface. The H_RESET
operation will unconditionally cause all INTR pins to
become inactive. (Note that there may be either 2 or 4
INTR pins, depending upon the JTAGSEL pin setting.)
The H_RESET operation will unconditionally cause the
HOLD signal to become de-asserted.
H_RESET will reset T-MAU to Link Fail state.
H_RESET is generated by proper assertion of either
the RESET or RESET pin, depending upon the mode
that has been selected through the LB/VESA pin.
S_RESET
S_RESET = SOFTWARE_RESET is a PCnet-32
RESET operation that has been created by a read ac-
cess to the RESET REGISTER which is located at
offset 14h from the PCnet-32 controller I/O base
address.
LED
Output
Default
Interpretation
Default
Drive
Enable
Default
Output
Polarity
LNKST
Link Status
Enabled
Active LOW
LED1
Receive
Enabled
Active LOW
LED2
Receive Polarity
Enabled
Active LOW
LEDPRE3
Transmit
Enabled
Active LOW
LNKST
LNKST E
RCVM
RCVM E
XMT
XMT E
RXPOL
RXPOL E
RCV
RCV E
JAB
JAB E
COL
COL E
To
Pulse
Stretcher
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
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