參數(shù)資料
型號(hào)： MII-300GP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, MICROPROCESSOR, PGA296
封裝： SPGA, 296 PIN
文件頁(yè)數(shù)： 43/257頁(yè)
文件大?。?/td> 1234K
代理商： MII-300GP
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PRELIMINARY
3-15
3
Signal Descriptions
3.2.10 Cache Control
The cache control signals (EWBE#, FLUSH#,
KEN#, PCD, PWT, WB/WT#) are used to indi-
cate cache status and control caching activity.
External Write Buffer Empty (EWBE#) is an
active low input driven by the system to indi-
cate when there are no pending write cycles in
the external system. The M II CPU samples
EWBE# during write cycles (I/O and memory)
only. If EWBE# is not asserted, the processor
delays all subsequent writes to on-chip cache
lines in the “exclusive” or “modified” state until
EWBE# is asserted. Regardless of the state of
EWBE#, all writes to the on-chip cache are
delayed until any previously issued external
write cycle is complete. This ensures that
external write cycles occur in program order
and is referred to as “strong write ordering”. To
enhance performance, “weak write ordering”
may be allowed for specific address regions
using the Address Region Registers (ARRs) and
Region Control Registers (RCRs).
Cache Flush (FLUSH#) is a falling edge sensi-
tive input that forces the processor to
write-back all dirty data in the cache and then
invalidate the entire cache contents. FLUSH#
need only be asserted for a single clock but
must meet specified setup and hold times to
guarantee recognition at a particular clock
edge.
Once FLUSH# is sampled active, the M II CPU
begins the cache flush sequence after comple-
tion of the current instruction. External inter-
rupts and additional FLUSH# requests are
ignored while the cache flush is in progress.
However, cache inquiry cycles are permitted
during the flush sequence. The M II CPU issues
a special flush acknowledge cycle to indicate
completion of the flush sequence. If the
processor is in a halt or shutdown state,
FLUSH# is recognized and the M II CPU
returns to the halt or shutdown state following
completion of the flush sequence. If FLUSH# is
active at the falling edge of RESET, the
processor enters three state test mode.
Cache Enable (KEN#) is an active low input
which indicates that the data being returned
during the current cycle is cacheable. When the
M II CPU is performing a cacheable code fetch
or memory data read cycle and KEN# is
sampled asserted, the cycle is transformed into
a cache line fill (4 transfer burst cycle) or a
“1+4” cache line fill. KEN# is sampled with the
first asserted BRDY# or NA# for the cycle. I/O
accesses, locked reads, system management
memory accesses and interrupt acknowledge
cycles are never cached.
Page Cache Disable (PCD) is an active high
output that reflects the state of the PCD page
attribute bit in the page table entry or the
directory table entry. If paging is disabled or for
cycles that are not paged, the PCD pin is driven
low. PCD is masked by the cache disable (CD)
bit in CR0 (driven high if CD=1) and floats
during bus hold states.
Page Write Through (PWT) is an active high
output that reflects the state of the PWT page
attribute bit in the page table entry or the direc-
tory table entry. During non-paging cycles, and
while paging is disabled the PWT pin is driven
low. If PWT is asserted, PWT takes priority over
the WB/WT# input. If PWT is asserted for
either reads or writes, the cache line is saved in,
or remains in, the shared (write-through) state.
PWT floats during bus hold states.
相關(guān)PDF資料
PDF描述
MJ10000 20 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ1000 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ1001 10 A, 80 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ10022 40 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AE
MJ3000 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA
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