
6
-4
2
P
R
E
L
IM
IN
A
R
Y
C
P
U
In
s
tr
u
cti
o
n
S
e
t
S
u
m
a
r
y
PUNPCKHBW Unpack High Packed Byte
Data to Packed Words
MMX Register 2 to MMX Register1
Memory to MMX Register
5
30F68 [11 mm1 mm2]
0F68 [11 mm reg]
MMX reg 1 [byte] <--interleave-- MMX reg 1 [up byte], MMX reg 2 [up byte]
MMX reg [byte] <--interleave-- memory [up byte], MMX reg [up byte]
1/1
PUNPCKHDQ Unpack High Packed Dword
Data to Qword
MMX Register 2 to MMX Register1
Memory to MMX Register
5
40F6A [11 mm1 mm2]
0F6A [11 mm reg]
MMX reg 1 [dword] <--interleave-- MMX reg 1 [up dword], MMX reg 2 [up dword]
MMX reg [dword] <--interleave-- memory [up dword], MMX reg [up dword]
1/1
PUNPCKHWD Unpack High Packed Word
Data to Packed Dwords
MMX Register 2 to MMX Register1
Memory to MMX Register
5
50F69 [11 mm1 mm2]
0F69 [11 mm reg]
MMX reg 1 [word] <--interleave-- MMX reg 1 [up word], MMX reg 2 [up word]
MMX reg [word] <--interleave-- memory [up word], MMX reg [up word]
1/1
PUNPCKLBW Unpack Low Packed Byte
Data to Packed Words
MMX Register 2 to MMX Register1
Memory to MMX Register
5
60F60 [11 mm1 mm2]
0F60 [11 mm reg]
MMX reg 1 [word] <--interleave-- MMX reg 1 [low byte], MMX reg 2 [low byte]
MMX reg [word] <--interleave-- memory [low byte], MMX reg [low byte]
1/1
PUNPCKLDQ Unpack Low Packed Dword
Data to Qword
MMX Register 2 to MMX Register1
Memory to MMX Register
5
70F62 [11 mm1 mm2]
0F62 [11 mm reg]
MMX reg 1 [word] <--interleave-- MMX reg 1 [low dword], MMX reg 2 [low dword]
MMX reg [word] <--interleave-- memory [low dword], MMX reg [low dword]
1/1
PUNPCKLWD Unpack Low Packed Word
Data to Packed Dwords
MMX Register 2 to MMX Register1
Memory to MMX Register
5
80F61 [11 mm1 mm2]
0F61 [11 mm reg]
MMX reg 1 [word] <--interleave-- MMX reg 1 [low word], MMX reg 2 [low word]
MMX reg [word] <--interleave-- memory [low word], MMX reg [low word]
1/1
PXOR Bitwise XOR
MMX Register 2 to MMX Register1
Memory to MMX Register
5
9
0FEF [11 mm1 mm2]
0FEF [11 mm reg]
MMX Reg 1 [qword] <--logic exclusive OR-- MMX Reg 1 [qword], MMX Reg 2 [qword]
MMX Reg [qword] <--logic exclusive OR-- memory[qword], MMX Reg [qword]
1/1
Table 6-25. M II Processor MMX Instruction Set Clock Count Summar y (Continued)
MMX INSTRUCTIONS
OPCODE
OPERATION
CLOCK
COUNT
LATENCY/
THROUGHPUT