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參數(shù)資料
| 型號(hào)： | MII-300GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, PGA296 |
| 封裝： | SPGA, 296 PIN |
| 文件頁(yè)數(shù)： | 31/257頁(yè) |
| 文件大?。?/td> | 1234K |
| 代理商： | MII-300GP |
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PRELIMINARY
3-5
3
Signal Description Table
NA#
Next Address requests the next pending bus cycle address and cycle
definition information. If either the current or next bus cycle is a locked cycle,
a line replacement, a write-back cycle, or if there is no pending bus cycle, the
M II CPU does not start a pipelined bus cycle regardless of the state of NA#.
Input
Page 3-13
NMI
Non-Maskable Interrupt Request forces the processor to suspend
execution of the current instruction stream and begin execution of an NMI
interrupt service routine.
Input
Page 3-14
PCD
Page Cache Disable reflects the state of the PCD page attribute bit in the
page table entry or the directory table entry. If paging is disabled, or for
cycles that are not paged, the PCD pin is driven low. PCD is masked by the
cache disable (CD) bit in CR0, and floats during bus hold states.
Output
Page 3-15
PCHK#
Data Parity Check indicates that a data bus parity error has occurred
during a read operation. PCHK# is only valid during the second clock
immediately after read data is returned to the M II CPU (BRDY# asserted)
and is inactive otherwise. Parity errors signaled by a logic low on PCHK#
have no effect on processor execution.
Output
Page 3-10
PM0-PM1
Performance Monitor indicate an at least one overflow or event
occurred in the associated Performance Monitor Register (0-1).
Output
Page 3-20
PWT
Page Write-Through reflects the state of the PWT page attribute bit in the
page table entry or the directory table entry. PWT pin is negated during cycles
that are not paged, or if paging is disabled. PWT takes priority over
WB/WT#.
Output
Page 3-15
RESET
Reset suspends all operations in progress and places the M II CPU into a
reset state. Reset forces the CPU to begin executing in a known state. All data
in the on-chip caches is invalidated.
Input
Page 3-7
SCYC
Split Locked Cycle indicates that the current bus cycle is part of a
misaligned locked transfer. SCYC is defined for locked cycles only. A
misaligned transfer is defined as any transfer that crosses an 8-byte boundary.
Output
Page 3-11
SMI#
SMM Interrupt forces the processor to save the CPU state to the top of
SMM memory and to begin execution of the SMI service routine at the
beginning of the defined SMM memory space. An SMI is a higher-priority
interrupt than an NMI.
Input
Page 3-14
SMIACT#
SMM Interrupt Active indicates that the processor is operating in System
Management Mode. SMIACT# does not float during bus hold states.
Output
Page 3-13
SUSP#
Suspend Request requests that the CPU enter suspend mode. SUSP# is
ignored following RESET and is enabled by setting the SUSP bit in CCR2.
Input
Page 3-19
SUSPA#
Suspend Acknowledge indicates that the M II CPU has entered low-power
suspend mode. SUSPA# floats following RESET and is enabled by setting the
SUSP bit in CCR2.
Output
Page 3-19
TCK
Test Clock (JTAG) is the clock input used by the M II CPU’s boundary scan
(JTAG) test logic.
Input
Page 3-22
TDI
Test Data In (JTAG) is the serial data input used by the M II CPU’s
boundary scan (JTAG) test logic.
Input
Page 3-22
Table 3-1. M II CPU Signals Sorted by Signal Name (Continued)
Signal
Name
Description
I/O
Reference
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MJ10000 | 20 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
| MJ1000 | 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
| MJ1001 | 10 A, 80 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
| MJ10022 | 40 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AE |
| MJ3000 | 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MII400-12E4 | 功能描述:分立半導(dǎo)體模塊 IGBT MODULE 1200V, 400A RoHS:否 制造商:Infineon Technologies 產(chǎn)品:Thyristor Power Modules 類型:Phase Controls 安裝風(fēng)格:Screw 封裝 / 箱體:DT61 封裝: |
| MII-400GP 95MHZ2.2V | 制造商:CYRIX 功能描述: |
| MII75-12A3 | 功能描述:分立半導(dǎo)體模塊 75 Amps 1200V RoHS:否 制造商:Infineon Technologies 產(chǎn)品:Thyristor Power Modules 類型:Phase Controls 安裝風(fēng)格:Screw 封裝 / 箱體:DT61 封裝: |
| MI-IAM | 制造商:VICOR 制造商全稱:Vicor Corporation 功能描述:Military Input Attenuator Modules |
| MIIC5271 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:UCAP NEGATIVE LOW DROPOUT REGULATOR |
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