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參數(shù)資料
| 型號(hào)： | MII-300GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, PGA296 |
| 封裝： | SPGA, 296 PIN |
| 文件頁(yè)數(shù)： | 30/257頁(yè) |
| 文件大小： | 1234K |
| 代理商： | MII-300GP |
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3-4
PRELIMINARY
Signal Description Table
Advanci ng the S tandar ds
FLUSH#
Cache Flush forces the M II CPU to flush the cache. External interrupts and
additional FLUSH# assertions are ignored during the flush. Cache inquiry
cycles are permitted during the flush.
Input
Page 3-15
HIT#
Cache Hit indicates that the current cache inquiry address has been found
in the cache (modified, exclusive or shared states). HIT# is valid two clocks
after EADS# is sampled active, and remains valid until the next cache inquiry
cycle.
Output
Page 3-18
HITM#
Cache Hit Modified Data indicates that the current cache inquiry address
has been found in the cache and dirty data exists in the cache line (modified
state). The M II CPU does not accept additional cache inquiry cycles while
HITM# is asserted. HITM# is valid two clocks after EADS#.
Output
Page 3-18
HLDA
Hold Acknowledge indicates that the M II CPU has responded to the
HOLD input and relinquished control of the local bus. The M II CPU
continues to operate during bus hold as long as the on-chip cache can satisfy
bus requests.
Output
Page 3-17
HOLD
Hold Request indicates that another bus master has requested control of the
CPU’s local bus.
Input
Page 3-16
IGNNE#
Ignore Numeric Error forces the M II CPU to ignore any pending
unmasked FPU errors and allows continued execution of floating point
instructions.
Input
Page 3-19
INTR
Maskable Interrupt forces the processor to suspend execution of the
current instruction stream and begin execution of an interrupt service
routine. The INTR input can be masked (ignored) through the IF bit in the
Flags Register.
Input
Page 3-14
INV
Invalidate Request is sampled with EADS# to determine the final state of
the cache line in the case of a cache inquiry hit. An asserted INV directs the
processor to change the state of the cache line to “invalid”. A negated INV
directs the processor to change the state of the cache line to “shared.”
Input
Page 3-18
KEN#
Cache Enable allows the data being returned during the current cycle to be
placed in the CPU’s cache. When the M II CPU is performing a cacheable
code fetch or memory data read cycle (CACHE# asserted), and KEN# is
sampled asserted, the cycle is transformed into a 32-byte cache line fill. KEN#
is sampled with the first asserted BRDY# or NA# for the cycle.
Input
Page 3-15
LOCK#
Lock Status indicates that other system bus masters are denied access to the
local bus. The M II CPU does not enter the bus hold state in response to
HOLD while LOCK# is asserted.
Output
Page 3-11
M/IO#
Memory/IO Status. If high, indicates that the current bus cycle is a
memory cycle (read or write). If low, indicates that the current bus cycle is an
I/O cycle (read or write, interrupt acknowledge, or special cycle).
Output
Page 3-11
Table 3-1. M II CPU Signals Sorted by Signal Name (Continued)
Signal
Name
Description
I/O
Reference
相關(guān)PDF資料 |
PDF描述 |
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| MJ10000 | 20 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
| MJ1000 | 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
| MJ1001 | 10 A, 80 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
| MJ10022 | 40 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AE |
| MJ3000 | 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| MII75-12A3 | 功能描述:分立半導(dǎo)體模塊 75 Amps 1200V RoHS:否 制造商:Infineon Technologies 產(chǎn)品:Thyristor Power Modules 類型:Phase Controls 安裝風(fēng)格:Screw 封裝 / 箱體:DT61 封裝: |
| MI-IAM | 制造商:VICOR 制造商全稱:Vicor Corporation 功能描述:Military Input Attenuator Modules |
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