參數(shù)資料
型號(hào)： MII-300GP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, MICROPROCESSOR, PGA296
封裝： SPGA, 296 PIN
文件頁(yè)數(shù)： 223/257頁(yè)
文件大?。?/td> 1234K
代理商： MII-300GP
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2-37
2
PRELIMINARY
System Register Set
Inverted Region (INV_RGN). Setting
INV-RGN applies the controls in RCRx to all the
memory addresses outside the specified address
region ARRx. This bit effects RCR0-RCR6 and
not RCR7.
Write Through (WT). Setting WT defines the
address region as write-through instead of
write-back, assuming the region is cacheable.
Regions where system ROM are loaded (shad-
owed or not) should be defined as write-
through. This bit works in conjunction with the
CR0_NW and PWT bits and the WB/WT# pin
to determine write-through or write-back
cacheability.
Write Gathering (WG). Setting WG enables
write gathering for the associated address
region. Write gathering allows multiple byte,
word, or Dword sequential address writes to
accumulate in the on-chip write buffer. As
instructions are executed, the results are placed
in a series of output buffers. These buffers are
gathered into the final output buffer.
When access is made to a non-sequential mem-
ory location or when the 8-byte buffer becomes
full, the contents of the buffer are written on the
external 64-bit data bus. Performance is
enhanced by avoiding as many as seven memory
write cycles.
WG should not be used on memory regions that
are sensitive to write cycle gathering. WG can be
enabled for both cacheable and non-cacheable
regions.
Weak Locking (WL). Setting WL enables
weak locking for the associated address region.
During weak locking all bus cycles are issued
with the LOCK# pin negated (except when page
table access occur and during interrupt
acknowledge cycles.)
Interrupt acknowledge cycles are executed as
locked cycles even though LOCK# is negated.
With WL set previously non-cacheable locked
cycles are executed as unlocked cycles and
therefore, may be cached, resulting in higher
CPU performance.
Note that the NO_LOCK bit globally performs
the same function that the WL bit performs on
a single address region. The NO_LOCK bit of
CCR1 enables weak locking for the entire
address space. The WL bit allows weak locking
only for specific address regions. WL is inde-
pendent of the cacheability of the address
region.
Cache Disable (CD). Cache Disable - If set,
defines the address region as non-cacheable.
This bit works in conjunction with the CR0_CD
and PCD bits and the KEN# pin to determine
line cacheability. Whenever possible, the
ARR/RCR combination should be used to define
non-cacheable regions rather than using exter-
nal address decoding and driving the KEN# pin
as the M II can better utilize its advanced tech-
niques for eliminating data dependencies and
resource conflicts with non-cacheable regions
defined on-chip.
相關(guān)PDF資料
PDF描述
MJ10000 20 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ1000 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ1001 10 A, 80 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ10022 40 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AE
MJ3000 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA
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