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| 型號(hào)： | MII-300GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, PGA296 |
| 封裝： | SPGA, 296 PIN |
| 文件頁(yè)數(shù)： | 20/257頁(yè) |
| 文件大?。?/td> | 1234K |
| 代理商： | MII-300GP |
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2-85
2
PRELIMINARY
Virtual 8086 Mode
Virtual 8086 Mode
2-85
2.18
Virtual 8086 Mode
Both real mode and virtual 8086 (V86) mode
are supported by the M II CPU allowing execu-
tion of 8086 application programs and 8086
operating systems. V86 mode allows the
execution of 8086-type applications, yet still
permits use of the M II CPU paging mecha-
nism. V86 tasks run at privilege level 3.
When loaded, all segment limits are set to
FFFFh (64K) as in real mode.
2.18.1 V86 Memory
Addressing
While in V86 mode, segment registers are used
in an identical fashion to real mode. The
contents of the segment register are multiplied
by 16 and added to the offset to form the
segment base linear address. The M II CPU
permits the operating system to select which
programs use the V86 address mechanism and
which programs use protected mode
addressing for each task.
The M II CPU also permits the use of paging
when operating in V86 mode. Using paging,
the 1-MByte memory space of the V86 task can
be mapped to anywhere in the 4-GByte linear
memory space of the M II CPU.
The paging hardware allows multiple V86
tasks to run concurrently, and provides protec-
tion and operating system isolation. The
paging hardware must be enabled to run
multiple V86 tasks or to relocate the address
space of a V86 task to physical address space
greater than 1 MByte.
2.18.2 V86 Protection
All V86 tasks operate with the least amount of
privilege (level 3) and are subject to all of the
M II CPU protected mode protection checks. As
a result, any attempt to execute a privileged
instruction within a V86 task results in a
general protection fault.
In V86 mode, a slightly different set of instruc-
tions are sensitive to the I/O privilege level
(IOPL) than in protected mode. These instruc-
tions are: CLI, INT n, IRET, POPF, PUSHF, and
STI. The INT3, INTO and BOUND variations
of the INT instruction are not IOPL sensitive.
2.18.3 V86 Interrupt Handling
To fully support the emulation of an 8086-type
machine, interrupts in V86 mode are handled
as follows. When an interrupt or exception is
serviced in V86 mode, program execution
transfers to the interrupt service routine at
privilege level 0 (i.e., transition from V86 to
protected mode occurs) and the VM bit in the
EFLAGS register is cleared. The protected
mode interrupt service routine then deter-
mines if the interrupt came from a protected
mode or V86 application by examining the VM
bit in the EFLAGS image stored on the stack.
The interrupt service routine may then choose
to allow the 8086 operating system to handle
the interrupt or may emulate the function of
the interrupt handler. Following completion
of the interrupt service routine, an IRET
instruction restores the EFLAGS register
(restores VM=1) and segment selectors and
control returns to the interrupted V86 task.
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| MJ10000 | 20 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
| MJ1000 | 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA |
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