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| 型號(hào)： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁(yè)數(shù)： | 98/146頁(yè) |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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86
8-Bit Bulky
BDIF[2:0]
COMMENT
011
8-bit bulky mode
101
Reset
111
NOTES:
8-bit data of last block on packet
1. Any signal setting not included in the table is reserved.
2. Signal values should not be modified during data transfer.
16-Bit Bulky
BDIF[2:0]
COMMENT
000
8-bit data except last block on packet (lower)
010
16-bit bulky mode
011
8-bit bulky mode
100
8-bit data of last block on packet (lower)
101
Reset
110
16-bit data of last block on packet
111
NOTES:
8-bit data of last block on packet
1. Any signal setting not included in the table is reserved.
2. Signal values should not be modified during data transfer.
A written packet is automatically divided into the length specified by DTx header3, and is packetized.
Addresses specified on DTx header[1:2] are increased by the length of the data on each transmission. Also,
the last 3 bits of tLabel are incremented.
Each time an auto-divided packet transmission completes, DTAval is set and an appropriate
acknowledgement is displayed on DTxAck.
When a packetizer stops at the completion of all block data transmission or with some error, a DTFEnd
interrupt is created and its result is displayed on DTFSt(B0h).
8.4.2
Packet Receipt With DRF
By clearing the DRDSel bit on DMA control (90h), a packet stored in the DRF can be received. Data can not be read
with the DMA I/F in this case. When DRHStr in DMA control (90h) is set, the header of the packet is detached, and
the host reads only the data section with DRF data (ACh). The detached header is stored in DRF header[0:3]
(D0hDCh). When DRHStr is not set, the entire packet will be read. The format for this is the same as reading from
ARF.
Types of packets received by the DRF are:
Self-ID packet
Ordinary packet
Response packets to request packets from the DTF
Write request with specified address (direct mode)
Packetizer
Specified as a default
8.4.2.1 Self-ID Packet
Set both RXSId (08h, bit 1) and RSIsel (08h, bit 2) to 1 for the DRF to receive self-ID packets.
8.4.2.2 Response Packet to Request Packets From the DTF
To receive response packets to request packets from the DTF, set DTSpDis (90h, bit 7) to 0. This automatically sets
the expected values of the response packets. The DRF receives responses accordingly.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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