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參數(shù)資料
| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 34/146頁 |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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38
BITS
15
16
ACRONYM
StErpkt
SplTrEn
DIR
R/W
R/W
DESCRIPTION
Store error packets. When StErpkt is set to1, packets with any errors are stored.
Split transaction enable. When SplTrEn is set to 1, split transactions are enabled. The ATF timer attempts a
split transaction for the received ack_pending and cannot transmit any packets until the response packet
is received or a split-time out occurs. When SplTrEn is set to 0, split transactions are disabled. This bit
defaults to 1 and is unaffected by a bus reset.
Automatic retry enable. When set to 1, the ATF retries automatically when ack_busy_X, ack_busy_A or
ack_busy_B is received. This bit defaults to 1 and is unaffected by a bus reset.
17
RetryEn
R/W
18
Ackpnd
R/W
Ack pending enable. When Ackpnd is set to 1, the receiver sends ack_pending instead of ack_complete to
the write request packets. When Ackpnd is set to 0, the receiver sends ack_complete to the write request
packets.
Management ack_Conflict_Error enable. When MAAckConf is set to 1, ack_conflict_error is sent instead
of ack_busy when MagtBsy at 44h bit 1 is set to 1. When MAAckConf is set to 0, ack_busy is sent. This bit
is the same as MAAckConf at 18h bit 14.
Cycle master. When CyMas is set to 1 and this chip is the root PHY, the cycle master function is enabled.
When CyMas is set to 0, the cyclemaster function is disabled. This bit defaults to 1 and is unaffected by a
bus reset.
Reserved
Cycle-timer enable. When CyTmrEn is set to 1, the cycle_offset field increments. This bit defaults to 1 and
is unaffected by a bus reset.
19
MAAckConf
R/W
20
CyMas
R/W
21
22
Reserved
CyTmrEn
N/A
R/W
23
DMclr
S/C
DMA block clear. When DMClr is set to 1, all the states in the DMA block are reset synchronously. Clear the
DMA, DTF, and DRF prior to clearing the DMA.
24
RxUnexp
R/W
Received unexpected response packets. When set to 1, unexpected response packets are received and
written to the ARF or the DRF. When set to 0, unexpected response packets are not received.
25
RUEsel
R/W
Receive unexpected response packets select. Select either the ARF or DRF to place the unexpected
response packets. When RxUnexp is set to 1 and RUEsel is set to 1, the unexpected response packets,
such as a write request packet to a read-only register or a read request to a write-only register, are written
to the DRF.
When RxUnexp is set to 1 and RUEsel is set to 0, the unexpected response packets are written to ARF.
When RxUnexp is set to 0, RUEsel is invalid.
Priority budget counter. Prio_Budget value loaded to the priority budget counter.
2631
Prio_Budget
R/W
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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