參數(shù)資料
型號: TSB43AA82A1
廠商: Texas Instruments, Inc.
英文描述: 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述: 1394綜合物理層和鏈路層控制器(1394集成物理層和鏈路層控制器)
文件頁數(shù): 16/146頁
文件大?。?/td> 597K
代理商: TSB43AA82A1
16
1.4.3
Physical Layer (continued)
TERMINAL
PGE NO.
95
96
I/O
DESCRIPTION
NAME
GGW NO.
G17
G16
TPA1N
TPA1P
I/O
Twisted-pair cable-A differential signal terminals. Board traces from each pair of
short as possible to the external load resistors and to the cable connector.
TPA2N
TPA2P
106
107
C17
C16
I/O
positive and negative differential signal terminals must match and be kept as
TPB1N
TPB1P
91
92
J17
J16
I/O
Twisted-pair cable-B differential signal terminals. Board traces from each pair of
short as possible to the external load resistors and to the cable connector.
TPB2N
TPB2P
102
103
E17
E16
I/O
positive and negative differential signal terminals must match and be kept as
TPBIAS1
TPBIAS2
97
108
G15
B17
O
Twisted pair bias output. This provides the 1.86-V nominal bias voltage needed
for proper operation of the twisted-pair cable drivers and receivers, and for
signaling to the remote nodes that there is an active cable connection. Each of
these terminals, except for an unused port, must be decoupled with a 1.0-
μ
F
capacitor to ground. For the unused port, this terminal can be left unconnected.
XI
XO
115
116
A13
A12
Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel reso-
nant fundamental mode crystal. The optimum values for the external shunt ca-
pacitors are dependent on the specifications of the crystal used.
1.4.4
Test Interface
TERMINAL
PGE NO.
I/O
DESCRIPTION
NAME
GGW NO.
TEST[7:0]
129, 127, 125,
124, 122, 121,
120, 119
C8, A8, C9,
A9, C10, A10,
A11, B11
I/O
Test data lines. The test data lines are used in manufacturing test and is tied low in
normal/operational mode.
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