參數(shù)資料
型號： TSB43AA82A1
廠商： Texas Instruments, Inc.
英文描述： 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述： 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器）
文件頁數(shù)： 40/146頁
文件大?。?/td> 597K
代理商： TSB43AA82A1
314
3.4.14 MRF Status Register at 38h
This register defaults to 1000 0000h and, except for the bits specified, is cleared on a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
MRFFul
R/O
MRF full flag. When the MRF is full, MRFFul is set to 1 and writes are ignored. Otherwise, MRFFul is set to
0. This bit defaults to 0 and is set to 0 on a bus reset.
1
MRFAFl
R/O
MRF almost-full flag. While the MRF can receive only one more quadlet, MRFAF1 is set to 1. Otherwise,
MRFAFl is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
2
MRFAEm
R/O
MRF almost-empty flag. While the MRF contains only one quadlet, MRFAEm is set to 1. Otherwise,
MRFAEm is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
3
MRFEmp
R/O
MRF empty flag. While the MRF is empty, MRFEmp is set to 1. Otherwise, MRFEmp is set to 0. This bit
defaults to 1 and is set to 1 on a bus reset.
46
Reserved
N/A
Reserved
715
MRFThere
R/O
MRF there. The number of quadlets received in the MRF. This bit defaults to 0 and is set to 0 on a bus reset.
16
MRFCD
R/O
MRF control bit. When the first quadlet of a packet is read from the MRF data (84h) register, MRFCD is set
to 1. This bit defaults to 0 and is set to 0 on a bus reset.
1718
Reserved
N/A
Reserved
19
MRFClr
S/C
MRF clear control bit. When MRFClr is set to 1, the MRF is cleared. This bit defaults to 0 and is cleared on a
bus reset.
2031
Reserved
N/A
Reserved
3.4.15 CTQ Status Register at 3Ch
This register defaults to 1000 000Fh and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
CTQFul
R/O
CTQ full flag. While the CTQ is full, CTQFul is set to 1 and writes are ignored. Otherwise, CTQFul is set to
0. Note: (CTQ – 1) size is displayed. This bit defaults to 0 and is set to 0 on a bus reset.
1
CTQAFl
R/O
CTQ almost-full flag. While the CTQ can accept only one more quadlet write, CTQAFl is set to 1.
Otherwise, CTQAFl is set to 0. Note: This bit is set to 0 after 3 quadlets are written (1). This bit defaults to 0
and is set to 0 on a bus reset.
2
CTQAEm
R/O
CTQ almost-empty flag. While the CTQ has only one quadlet in it, CTQAEm is set to 1. Otherwise,
CTQAEm is set to 0. Note: This bit is set to 0 after writing 2 quadlets. This bit defaults to 0 and is set to 0 on a
bus reset.
3
CTQEmp
R/O
CTQ empty flag. When the CTQ is empty, CTQEmp is set to 1. Otherwise, CTQEmp is set to 0. This bit
defaults to 1 and is set to 1 on a bus reset.
4
Reserved
N/A
Reserved
5
CTQ1Av
R/O
CTQ1 available flag. CTQ can accept one more packet (3 quadlets). This bit defaults to 0 and is set to 0 on
a bus reset.
618
Reserved
N/A
Reserved
19
CTQClr
S/C
CTQ clear control bit. When CTQClr is set, the CTQ is cleared. This bit clears itself after the CTQ is
cleared. This bit defaults to 0 and is set to 0 on a bus reset.
2022
Reserved
N/A
Reserved
2331
CTQ_Size
R/W
CTQ size control bits. CTQ_Size is equal to the CTQ size number in quadlets. This field defaults to Fh and
remains unaffected by a bus reset.
NOTE 1: Provides only 3 quadlets.
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