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| 型號(hào)： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁(yè)數(shù)： | 63/146頁(yè) |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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337
3.4.47.1 DRx Header Register 0 at E8h
BITS
03
ACRONYM
STAT
DIR
R/O
DESCRIPTION
DRF packetizer transaction complete state. STAT is the state of a completed DRF transaction.
0h
The request block transaction from the DRF was completed successfully.
1h
An ack_pending was received and the transaction is a split transaction.
2h
The acknowledgement (except ack_complete, ack_busy_X, and ack_pending) was returned in
response to the request packet.
3h
Reserved
4h
The transaction was stopped because of a page table fetch problem.
5h-6h
Reserved
7h
The request packet was transmitted Retry_Limit times.
8h-9h
Reserved
Ah
The response packet was received but rCode is not complete.
Bh
The response packet was not received in Split_Time.
Ch
The request packet was not sent because of a bus reset.
Dh
The request packet was removed because of RstTr or DTFClr at 90h.
Eh-Fh
Reserved
47
RESP
R/O
Specified status response received
810
Reserved
N/A
Reserved
11
AckErr
R/O
Ack error. Specifies whether the last ack received for the packet transmitted from DTF has any errors.
When the received ack has a parity error or length error, AckErr is set to 1. When the ack has no error or an
ack has not been received, AckErr is set to 0.
1215
Ack
R/O
Specified ack code received
1619
PSTAT
R/O
Specified page status code received. Refer to STAT for status.
2023
PRESP
R/O
Specified page status response received
2426
Reserved
N/A
Reserved
27
PAckErr
R/O
Page table ack error. Specifies whether the last ack received for the page table request has any errors.
When the received ack had a parity error or length error, PAckErr is set to 1. When the ack has no error or
an ack has not been received yet, PAckErr is set to 0.
2831
PAck
R/O
Specified page ack code received.
3.4.47.2 DRx Header Register 1 at ECh
BITS
ACRONYM
DIR
DESCRIPTION
015
DRx page number
R/O
DRx page number. Specifies the current page number used during packetization. It is incremented by one
each time the packetizer fetches a new page table. This number is set to 0 when the packetizer starts from
an initial state.
1631
Reserved
N/A
Reserved
3.4.47.3 DRx Header Register 2 at F0h
BITS
ACRONYM
DIR
DESCRIPTION
015
DRx page length
R/O
(Note)
DRx page length. Specifies the current page table value used during the current packetization.
1631
DRx page table hi
R/O
(Note)
DRx page table high. Specifies the current page table address used during the current packetization.
NOTE: R/W when DTPktz = 0
3.4.47.4 DRx Header Register 3 at F4h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRx page table lo
R/O
DRx page table low. Specifies the current page table address used during current packetization.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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