參數(shù)資料
型號： TSB43AA82A1
廠商： Texas Instruments, Inc.
英文描述： 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述： 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器）
文件頁數(shù)： 57/146頁
文件大?。?/td> 597K
代理商： TSB43AA82A1
331
3.4.40.2
99
DRF Control Register 1 at C4h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_BlockCount/
DRF_BlockSize
R/W
DRF receive block size in bytes / DRF receive block count.
When LngBlk in DMA control (90h) is set to 1, this value is DRF_BlockSize.
When LngBlk is set to 0, this value is DRF_BlockCount. DRF_BlockSize specifies the received blocksize
value. DRF_BlockCount specifies the number of received blocks. DRF_BlockCount is decremented
during reception automatically.
3.4.40.3 DRF Control Register 2 at C8h
BITS
ACRONYM
DIR
DESCRIPTION
016
DRF_destination_ID
R/W
DRF transfer destination ID. DRF_destination_ID specifies the transferred destination ID.
1731
DRF_destination_offset_hi
R/W
DRF transfer destination start offset high. DRF_destination_offset_hi specifies the transferred
destination offset high.
3.4.40.4 DRF Control Register 3 at CCh
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_destination_offset_lo
R/W
DRF receive destination start offset low. DRF_destination_offset_lo specifies the transferred
destination offset low.
3.4.41 DRF Header Registers at D0h, D4h, D8h, and DCh
If DRHStr at 90h bit 27 is set to 1, the stripped header is written to these registers. These registers default to
0000 0000h and are unaffected by a bus reset.
3.4.41.1 DRF Header Register 0 at D0h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_Header0
R/O
DRF Header0. First quadlet of received packet header in DRF. When DRHStr at 90h is set to 1, the host
can read the first header quadlet of a received packet header after the header has been copied into
DRF_Header0.
3.4.41.2 DRF Header Register 1 at D4h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_Header1
R/O
DRF Header1. Second quadlet of received packet header in DRF. When DRHStr at 90h is set to 1, the host
can read the second header quadlet of a received packet header after the header has been copied into
DRF_Header1.
3.4.41.3 DRF Header Register 2 at D8h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_Header2
R/O
DRF Header2. Third quadlet of received packet header in DRF. When DRHStr at 90h is set to 1, the host
can read the third header quadlet of a received packet header after the header has been copied into
DRF_Header2.
3.4.41.4 DRF Header Register 3 at DCh
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_Header3
R/O
DRF Header3. Fourth quadlet of received packet header in DRF. When DRHStr at 90h is set to 1, the host
can read the fourth header quadlet of a received packet header after the header has been copied into
DRF_Header3.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB43AA82AI 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products
TSB43AA82AIPGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82AIPGEEP 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGEG4 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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