參數(shù)資料
型號: TSB43AA82A1
廠商: Texas Instruments, Inc.
英文描述: 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述: 1394綜合物理層和鏈路層控制器(1394集成物理層和鏈路層控制器)
文件頁數(shù): 111/146頁
文件大?。?/td> 597K
代理商: TSB43AA82A1
911
9.4
Asynchronous Handshake Mode (Modes B, C, and F)
9.4.1
Request Transmission (Memory
TSB43AA82A) (Modes B, C, and F)
BDIBUSY
BDIEN
DATA8/16
BDIF[2:0]
0
1
F0
F1
The data needs to be specified by the BDIEN falling edge. Also, BDIEN needs to be asserted after confirming
BDIBUSY input is false.
A 16-bit bus data write can not cross over a 32-bit boundary.
9.4.2
Receiving Transmission (TSB43AA82A
Memory) (Modes B, C, and F)
BDOAVAIL
BDIEN
DATA8/16
BDIF[2:0]
1
0
F1
F0
The data is output by repeating BDOEN low and high. BDOEN is asserted after confirming the BDOAVAIL input is
true.
9.4.3
Timing Values (Modes B, C, and F)
Figure 97 shows the asynchronous mode expanded to better show signal timing. Table 98 shows timing values
for Figure 97.
BDIEN
BDOEN
tw(BDOENH)
tw(BDIENH)
tw(BDIENL)
tw(BDOENL)
Figure 97. Asynchronous Mode
Table 98. Asynchronous Mode
ITEM
TITLE
MIN
MAX
UNIT
tw(BDIENH)
tw(BDIENL)
tw(BDOENH)
tw(BDOENL)
BDIEN pulse duration on
25
ns
BDIEN pulse duration off
25
ns
BDOEN pulse duration on
25
ns
BDOEN pulse duration off
25
ns
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