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參數(shù)資料
| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 70/146頁 |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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44
Table 41. Block-Transmit Format Descriptions
FIELD NAME
DESCRIPTION
spd
This field indicates the speed at which this packet is to be sent.
00 = 100 Mbps
01 = 200 Mbps
10 = 400 Mbps
11 is undefined for this implementation.
tLabel
This field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This is
used to pair up a response packet with its corresponding request packet. See Section 4.2 for more information.
The retry code for this packet is:
00 = new
01 = retry_X
10 = retryA
11 = retryB.
rt
tCode
prior
destination ID
tCode is the transaction code for this packet. See Table 6-9 of IEEE 1394-1995 standard for more information.
The priority level for this packet. The value of the priority bits must be zero.
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the destination node address
of this packet.
The concatenation of these two fields addresses a quadlet in the destination node address space. This address must
be quadlet aligned (modulo 4). The upper four bits of the destination_offset_high field are used as the response code
for lock-response packets and the remaining bits are reserved.
For write requests and read responses, this field holds the data to be transferred. For write responses and read
requests, this field is not used and must not be written into the FIFO.
The number of bytes of data to be transmitted in the packet.
The block extended_tCode to be performed on the data in this packet. See Table 6-10 of the IEEE 1394-1995
standard for more information.
The data to be sent. If dataLength is 0, no data should be written into the FIFO for this field. Regardless of the
destination or source alignment of the data, the first byte of the block must appear in byte 0 of the first quadlet.
destination_offset_high
destination_offset_low
quadlet data
data_length
extended_tCode
block data
4.3.2
PHY Packet Common Format
The ATF is also used to transmit PHY configuration packets. The format of the transmitted PHY configuration packet
is shown in Figure 43 and a description of each field is shown in Table 42. The first quadlet is written to address
70h. The second quadlet is written to address 78h. The 00E0h in the first quadlet tells the link that this is the PHY
configuration packet. The 00E0h is then replaced with 0000h before the packet is transmitted to the PHY interface.
There is a possibility of a false header error on receipt of a PHY configuration packet. If the first 16 bits of a PHY
configuration packet match the destination identifier of a node (bus number and node number), the TSB43AA82A
issues a header error because the node misinterprets the PHY configuration packet as a data packet addressed to
the node.
Figure 4-3 is the PHY packet format. The following packet formats describe the PHY packet formats for the link-on,
ping, remote access, remote command, and resume packets.
0
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15
16 17
18 19
20 21
22 23
24 25
26 27
28 29
30 31
X
X
root_ID
R
T
Gap_cnt
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
Logical inverse of first quadlet
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 43. PHY Packet Format
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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