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| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 124/146頁 |
| 文件大小： | 597K |
| 代理商： | TSB43AA82A1 |
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112
port-to-port connection between bus segments. While in the suspended state, the port is unable to transmit or receive
data transaction packets. However, the port in the suspended state is capable of detecting connection status changes
and detecting incoming TPBIAS. When the port is suspended, all circuits except the bandgap reference generator
and bias detection circuits can be powered down, resulting in significant power savings. For additional details of
suspend/resume operation, see the P1394a specification. The use of suspend/resume is recommended for new
designs.
The port transmitter and receiver circuitry is disabled during power-down, during reset (when the XRESETP input
terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration
logic. The TPBIAS output is disabled during power-down, during reset, or when the port is disabled as commanded
by the internal LLC.
The CNA (cable-not-active) output terminal is asserted high when the twisted-pair cable port is not receiving incoming
bias (i.e., it is either disconnected or suspended), and can be used along with PD to determine when to power down
the TSB43AA82A. The CNA output is not debounced. When the PD bit is asserted high, the CNA detection circuitry
is enabled regardless of the previous state of the ports.
The LPS (link power status) terminal works to manage the power usage in the node. The LPS signal from the LLC
is used in conjunction with the LCtrl bit (see Section 11.2) to indicate the active/power status of the LLC. The LPS
signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is
controlled solely by the LPS input regardless of the state of the LCtrl bit).
11.2 PHY Internal Registers
There are 16 accessible internal registers for the PHY in the TSB43AA82A. The configuration of the registers at
addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8 through
Fh (the paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently selected.
The selected page is set in base register 7.
The configuration of the base registers is shown in Table 111, and corresponding field descriptions are given in
Table 112. The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as
Reserved
or
Rsvd
in the register configuration tables below) is read
as 0, but is subject to future usage. All registers in pages 2 through 6 are reserved.
Table 111. Base Register Configuration
Address
Bit Position
0
1
2
3
4
5
6
R
7
0000
Physical ID
CPS
0001
RHB
IBR
Gap_Count
0010
Extended (111b)
Num_Ports (00010b)
Delay (0000b)
0011
PHY_Speed (010b)
Rsvd
0100
LCtrl
C
Jitter (000b)
Pwr_Class
0101
WDIE
ISBR
CTOI
CPSI
STOI
PEI
EAA
EMC
0110
Reserved
0111
Page_select
Rsvd
Port_Select
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| TSL235(中文) | Programmable Light-To-Frequency Converter(光頻轉(zhuǎn)換器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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