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參數(shù)資料
| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 100/146頁 |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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88
8.4.4
Reading DRF Through the Bulky Interface
Set DRDSel (90h, bit 28) to 1 to output DRF data through the bulky interface.
The BDOF[2:0] attribute flag is output as follows:
BDOF[2:0]
COMMENT
010
16-bit data except last block on packet
011
8-bit data except last block on packet
100
No data
110
16-bit data of last on packet
111
8-bit data of last block on packet
8.4.4.1 Checking and Extracting Packet Data With a Microcontroller
With DRDSel (90h), Dpause (90h), and DRStPs (90h), output data from the bulky interface can be checked and/or
extracted by packet units. To check the content of a packet:
Set DRDSel (90h) to 0 and DRStPs (90h) to 1 to receive packets.
The microcontroller reads packet data through the CFR.
Change DRDSel to 1 to output data from the bulky interface.
When the next packet comes to the top of the DRF, Dpause is set to 1 and pauses the output.
Change DRFSel back to 0 and repeat this process.
To extract part of a packet:
Set DRDSel to 0, and DRStPs to 1 to receive packets.
The microcontroller reads packet data through the CFR.
Read the data to be extracted and switch DRDSel to 1 to extract data through the bulky interface. The rest
of the data is output to bulky interface.
When the next packet comes to the top of the DRF, Dpause will be set to 1 and will pause the output.
Change DRDSel back to 0 and repeat this process.
Once DRDSel is set to 1, the bulky interface can read additional data. Thus, if DRDSel were switched to
the CFR during the bulky interface output, the microcontroller does not read the correct data.
8.4.4.2 Deleting Packet Header/Trailer
Packet headers/trailers at the top of DRF are automatically copied to the DRF header [0:3] (D0h, D4h, D8h and DCh)
and DRF trailer (E0h) registers. After one packet has been read and the subsequent packet in the DRF comes in,
these registers are automatically updated.
Simultaneously, DRHUpdate Int (0Ch, bit 16) is created to show that the header was updated. Setting 1 on DRHStr
(90h, bit 27) strips a packet header/trailer from the DRF data. Only data is transferred through the CFR or bulky
interface.
8.4.4.3 Deleting Padding Data From the DRF Through the Bulky Interface
When RcvPad (94h, bit 28) is 1, data through the bulky interface contains padding data. To receive data without
padding data, set RcvPad to 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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