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參數(shù)資料
| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 94/146頁 |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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82
Table 81. DRF Block-Receive Format Descriptions
FIELD NAME
DESCRIPTION
The received packet goes into the DRF with each status.
0h
The request block transaction from the DRF completed successfully.
1h
An ack_pending was received and the transaction is a split transaction.
2h
The acknowledgement except ack_complete, ack_busy_X and ack_pending was returned inm response to the
request packet.
3h
Reserved
4h
The transaction was stopped because of a page table fetch problem.
5h6h
Reserved
7h
The request packet was transmitted Retry_Limit times.
8h9h
Reserved
Ah
The response packet was received but the rCode is not complete.
Bh
The response packet was not received in Split_Time.
Ch
The request packet was terminated because of a bus reset.
Dh
The request packet was removed because of RstTr or DTFClr at 90h.
EhFh
Reserved
This field indicates the speed at which this packet is to be sent. 00 = 100 Mbps, 01 = 200 Mbps, and 10 = 400 Mbps, and 11 is
undefined for this implementation.
This field holds the acknowledge sent by the receiver for this packet. (See Table 6-13 of the IEEE 1394-1995 standard).
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node address to which this
packet is being sent.
This field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This is used to
pair up a response packet with its corresponding request packet.
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode is the transaction code for this packet. (See Table 6-9 of the IEEE 1394-1995 standard).
The priority level for this packet. For cable implementation, the value of the bits must be zero. For backplane implementation,
see clauses 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995 standard.
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node address of the sender of
this packet.
This field is the response code for this packet. (See Table 6-11 of the IEEE 1394-1995 standard.)
For write requests, read responses, and locks, this field indicates the number of bytes being transferred. For read requests,
this field indicates the number of bytes of data to be read. A write-response packet does not use this field. Note that the
number of bytes does not include the header, only the bytes of block data.
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the IEEE 1394-1995 standard.
For write requests and read responses, this field holds the transferred data. For write responses and read requests, this field
is not present.
status
spd
ack
destination ID
tLabel
rt
tCode
prior
source ID
rCode
data_length
extended_tCode
block data
8.2.2
DTF Packet Format
The DTF packet format shown in Figure 82 describes the data format of the packet transmitted from the bulky data
interface. To transmit packets through the host, the 1394 headers and the data are loaded into the DTF interface
through registers A4hA8h by the host or bulky data interface. The first quadlet contains packet control information.
The second quadlet contains the bus and node number of the destination node, and the last 16 bits of the second
quadlet and the third quadlet contain the 48-bit quadlet-aligned destination offset address. The first 16 bits of the
fourth quadlet contain the size of the data in the packet. The remaining 16 bits of the fourth quadlet represent the
extended_tCode field. (See Table 6-10 of the IEEE 1394-1995
1
standard for more information on extended_tCodes.)
The block data, if any, follows the extended_tCode. Table 82 shows a description of each field.
1IEEE Std 1394-1395,
IEEE Standard for a High Performance Serial Bus
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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