參數(shù)資料
型號： TSB43AA82A1
廠商： Texas Instruments, Inc.
英文描述： 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述： 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器）
文件頁數(shù)： 46/146頁
文件大?。?/td> 597K
代理商： TSB43AA82A1
320
3.4.24 Transaction Timer Control Register at 60h
The timer manages all transactions from the request FIFOs. The transaction timer control register provides the status
and control of those transactions. This register defaults to FA00 0000h and, except for the specified bits, is unaffected
by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
DTTxEd
R/O
DTF transaction end. When the DTF transaction has completed, DTTxEd is set to 1. When the DTF
transaction begins, DTTxEd is set to 0. It defaults to 1 and is set to 1 on a bus reset.
1
DRTxEd
R/O
DRF transaction end. When the DRF transaction has completed, DRTxEd is set to 1. When the DRF
transaction begins, DRTxEd is set to 0. It defaults to 1 and is set to 1 on a bus reset.
2
ATTxEd
R/O
ATF transaction end. When the ATF transaction has completed, ATTxEd is set to 1. When the ATF
transaction begins, ATTxEd is set to 0. It defaults to 1 and is set to 1 on a bus reset.
3
MTTxEd
R/O
MTQ transaction end. When the MTQ transaction has completed, MTTxEd is set to 1. When the MTQ
transaction begins, MTTxEd is set to 0. It defaults to 1 and is set to 1 on a bus reset.
4
CTTxEd
R/O
CTQ transaction end. When the CTQ transaction has completed, CTTxEd is set to 1. When the CTQ
transaction begins, CTTxEd is set to 0. It defaults to 1 and is set to 1 on a bus reset.
5
Reserved
N/A
Reserved
6
ARTxEd
R/O
Autoresponse transaction end. When the autoresponse transaction has completed, ARTxEd is set to 1.
When the autoresponse transaction begins, ARTxEd is set to 0. It defaults to 1 and is set to 1 on a bus
reset.
7
Reserved
N/A
Reserved
8
DTErr
R/O
DTF transaction error. If the DTF transaction ends with errors or the DTF transaction is aborted (TxAbrt at
60h), DTErr is set to 1. Otherwise, if it ends without errors or the DTF transaction begins, DTErr is set to 0. It
defaults to 0 and is unaffected by a bus reset.
9
DRErr
R/O
DRF transaction error. If the DRF transaction ends with errors, DRErr is set to 1. Otherwise, if it ends
without errors or the DRF transaction begins, DRErr is set to 0. It defaults to 0 and is unaffected by a bus
reset.
10
ATErr
R/O
ATF transaction error. If the ATF transaction ends with errors, ATErr is set to 1. Otherwise, if it ends without
errors or the ATF transaction begins, ATErr is set to 0. This bit is defaults to 0 and is set to 0 on a bus reset.
11
MTErr
R/O
MTQ transaction error. If the MTQ transaction ends with errors, MTErr is set to 1. Otherwise, if it ends
without errors or the MTQ transaction begins, MTErr is set to 0. This bit is defaults to 0 and is set to 0 on a
bus reset.
12
CTErr
R/O
CTQ transaction error. If the CTQ transaction ends with errors, CTErr is set to 1. Otherwise, if it ends with
no errors or the CTQ transaction begins, CTErr is set to 0. This bit is defaults to 0 and is set to 0 on a bus
reset.
13
Reserved
N/A
Reserved
14
ARErr
R/O
Autoresponse transaction error. If the autoresponse transaction ends with errors, ARErr is set to 1.
Otherwise, if it ends with no errors or the autoresponse transaction begins, ARErr is set to 0. This bit is
defaults to 0 and is set to 0 on a bus reset.
15
Reserved
N/A
Reserved
16
DTRtry
R/O
DTF retry. When the DTF transaction begins retrying because of a received ack_busy_X, DTRtry is set to
1. When the retry transaction from the DTF ends and acknowledgements other than ack_busy_X, a retry
time-out, or a bus reset was received, DTRtry is set to 0. This bit is defaults to 0 and is set to 0 on a bus
reset.
17
DRRtry
R/O
DRF retry. When the DRF transaction begins retrying because of a received ack_busy_X, DRRtry is set to
1. When the retry transaction from DRF ends because acknowledgements other than ack_busy_X, a retry
time-out, or a bus reset was received, DRRtry is set to 0. This bit is defaults to 0 and is set to 0 on a bus
reset.
18
ATRtry
R/O
ATF retry. When the ATF transaction begins retrying because of a received ack_busy_X, ATRtry is set to 1.
When the retry transaction from ATF ends because acknowledgements other than ack_busy_X, a retry
time-out, or a bus reset was received, ATRtry is set to 0. This bit is defaults to 0 and is set to 0 on a bus
reset.
19
MTRtry
R/O
MTQ retry. When the MTQ transaction begins retrying because of a received ack_busy_X, MTRtry is set to
1.When the retry transaction from MTQ ends because acknowledgements other than ack_busy_X, a retry
time-out, or a bus reset was received, MTRtry is set to 0. This bit is defaults to 0 and is set to 0 on a bus
reset.
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TSB43AA82AIPGEEP 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGEG4 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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